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參數(shù)資料
| 型號： | A42MX16-3PL100ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 53/120頁 |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3PL100ES |
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38
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “000”. If CKDIV8 is programmed, CLKPS bits are reset to “011”,
giving a division factor of 8 at start up. This feature should be used if the selected clock source
has a higher frequency than the maximum frequency of the device at the present operating con-
ditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse
setting. The Application software must ensure that a sufficient division factor is chosen if the
selected clock source has a higher frequency than the maximum frequency of the device at the
present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.
Figure 3-14. System Clock Prescaler and Timer Clock Prescaler
3.8
Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU to save power.
The Atmel ATA6289 provides various sleep modes allowing the user to tailor the power con-
sumption to the application's requirements.
To enter one out of three sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, Sensor Noise Reduction, Power-down) will be activated by the SLEEP
instruction, see Table 3-11 on page 39 for details. If an enabled interrupt occurs while the MCU
is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the
start-up time, executes the interrupt routine, and resumes execution from the instruction follow-
ing SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes
up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the
Reset Vector.
Figure 3-13 on page 32 presents the different clock systems and their distribution and this is in
combination with Table 3-11 on page 39 helpful to select the appropriate sleep mode.
/2
CLT
CLTPS(2:0)
CLK
CL
/2
MUX
/2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-3PL100ES | 40MX and 42MX FPGA Families |
| A42MX36-3PL100ES | 40MX and 42MX FPGA Families |
| A42MX02-3PL100I | 40MX and 42MX FPGA Families |
| A42MX02-3PQ100 | 40MX and 42MX FPGA Families |
| A42MX04-3PQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3PL100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3PL84 | 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3PL84I | 功能描述:IC FPGA MX SGL CHIP 24K 84-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3PL84M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field Programmable Gate Array (FPGA) |
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