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參數(shù)資料
| 型號： | A42MX16-2CQ100ES |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:Stripped End Leads; Cable Length:5m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 74/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-2CQ100ES |
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57
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
Figure 3-23. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-
cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed
between and 1 system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 3-24. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
Figure 3-24. Synchronization when Reading a Software Assigned Pin Value
tpd,max
tpd,min
0xFF
0x00
XXX
in r17,PINx
XXX
INSTRUCTIONS
SYNC LATCH
r17
PINxn
SYSTEM CLK
0xFF
0x00
nop
in r17, PINx
SYSTEM CLK
INSTRUCTIONS
SYNC LATCH
PINxn
r17
t
pd
0xFF
out PORTx, r16
r16
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX24-2CQ100ES | Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:5m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes |
| A42MX36-2CQ100ES | Eurofast Cordset , Eurofast molded cordset RoHS Compliant: Yes |
| A42MX02-2CQ100I | Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:2m; No. of Contacts:3; No. of Positions:4 RoHS Compliant: Yes |
| A42MX02-2PQ100 | 40MX and 42MX FPGA Families |
| A42MX04-2PQ100 | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-2CQ100I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2CQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-2PL100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
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