參數(shù)資料
型號(hào)： A42MX16-2CQ100ES
廠商： Electronic Theatre Controls, Inc.
英文描述： Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:Stripped End Leads; Cable Length:5m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 47/120頁
文件大?。?/td> 854K
代理商： A42MX16-2CQ100ES
32
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.2
Clock Systems and their Distribution
Figure 3-13 presents the principal clock systems in the Atmel
AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the clocks
to modules not being used can be halted by using different sleep modes, as described in Section
3.8 “Power Management and Sleep Modes” on page 38. The clock systems are described in
detail below.
Figure 3-13. Clock Distribution
System Clock Prescaler Output - CLK
The system clock prescaler output signal (CLK) is used as clock sources for microcontroller, and
it will affect the clock frequency of the CPU and all synchronous peripherals. CLK
I/O, CLKCPU,
and CLK
Flash are divided by a factor as shown in Table 3-10 on page 37.
CPU Clock - CLK
CPU
The CPU clock is routed to parts of the system concerned with operation of the Atmel AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
I/O Clock - CLK
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and Ports.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted.
Flash Clock - CLK
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
Timer Clock Prescaler Output - CLT
The Timer clock allows the asynchronous Timer3/Counter3 to be clocked with a faster clock as
the I/O Clock (CLK
I/O). The Timer clock is usually active simultaneously with the CPU clock.
CLKI/O
Calibrated FRC
Oscillator
Calibrated SRC
Oscillator
System Prescaler
Reset Logic
Timer Clock
Prescaler
Multiplexer
General I/O
Modules
LF-Receiver
CPU Core
AVR Clock Module Unit
RAM
FRC
Timer/Counter
Flash and
EEPROM
CLT
SRC
CLKI/O
CLKFlash
CLKCPU
CLT
SCl
SCH
CLK
ECL
FRC
CL
SRC
External Clocks
SCH
相關(guān)PDF資料
PDF描述
A42MX24-2CQ100ES Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:5m; No. of Contacts:5; No. of Positions:5 RoHS Compliant: Yes
A42MX36-2CQ100ES Eurofast Cordset , Eurofast molded cordset RoHS Compliant: Yes
A42MX02-2CQ100I Sensor Cable Assembly; Connector Type A:M12 Plug; Connector Type B:M12 Receptacle; Cable Length:2m; No. of Contacts:3; No. of Positions:4 RoHS Compliant: Yes
A42MX02-2PQ100 40MX and 42MX FPGA Families
A42MX04-2PQ100 40MX and 42MX FPGA Families
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2CQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2CQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2PL100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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