參數(shù)資料
型號(hào)： A42MX16-2BG100
廠商： Electronic Theatre Controls, Inc.
英文描述： 40MX and 42MX FPGA Families
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 69/120頁
文件大?。?/td> 854K
代理商： A42MX16-2BG100
52
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.11.4
Pin Change Interrupt Control Register – PCICR
Bits 7..3 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2
Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.
Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT10..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT10..8 pins are enabled individually by the PCMSK1 Register.
Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
3.11.5
Pin Change Interrupt Flag Register – PCIFR
Bits 7..3 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 2 - PCIF2: Pin Change Interrupt Flag 2
When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set
(one). If the I-bit in SREG and the PCIE2 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT10..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter-
natively, the flag can be cleared by writing a logical one to it.
Bit
7
6543
210
-
PCIE2
PCIE1
PCIE0
PCICR
Read/Write
RRR
RR
R/W
Initial Value
0
0000
000
Bit
7
6
5
432
10
-
PCIF2
PCIF1
PCIF0
PCIFR
Read/Write
R/W
RR
R/W
Initial Value
0
000
00
相關(guān)PDF資料
PDF描述
A42MX24-2BG100 Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:15mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:18mm; Sensor Housing:Barrel
A42MX36-2BG100 40MX and 42MX FPGA Families
A42MX02-2BG100A Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:15mm; Sensor Output Type:NPN Transistor; Leaded Process Compatible:No; Peak Reflow Compatible (260 C):No; Sensing Face Diameter:18mm; Sensor Housing:Barrel
A42MX04-2BG100A 40MX and 42MX FPGA Families
A42MX09-2BG100A Inductive Proximity Sensor; Sensor Input Type:Inductive; Sensing Range Max:20mm; Sensor Output:AC/DC; Switch Terminals:Cable; Load Current Max:400mA; Sensing Face Diameter:30mm; Sensor Connection:2 m Cable; Sensor Housing:Barrel RoHS Compliant: Yes
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-2BG100A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2BG100B 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2BG100ES 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2BG100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-2BG100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
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