參數(shù)資料
型號(hào): A42MX16-1TQ100ES
廠商: Electronic Theatre Controls, Inc.
英文描述: Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:20V; Power Rating:175VA; Mounting Type:Chassis RoHS Compliant: Yes
中文描述: 40MX和42MX FPGA系列
文件頁(yè)數(shù): 75/120頁(yè)
文件大小: 854K
代理商: A42MX16-1TQ100ES
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58
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.12.2.5
Digital Input Enable and Sleep Modes
As shown in Figure 3-22 on page 55, the digital input signal can be clamped to ground at the
input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep
Controller in Power-down mode, Power-save mode, and Standby mode to avoid high power
consumption even if some input signals are left floating, or have an analog signal level close to
V
CC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various
other alternate functions as described in Section 3.12.3 “Alternate Port Functions” on page 59.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt
is not enabled, the corresponding External Interrupt Flag will be set when resuming from the
above mentioned Sleep mode, as the clamping in these sleep mode produces the requested
logic change.
3.12.2.6
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level. Even
though most of the digital inputs are disabled in the deep sleep modes as described above, float-
ing inputs should be avoided to reduce current consumption in all other modes where the digital
inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin is to enable the internal pull-up.
In this case, the pull-up will be disabled during reset. If low power consumption during reset is
important, it is recommended to use an external pull-up or pull-down. Connecting unused pins
directly to VCC or GND is not recommended, since this may cause excessive currents if the pin
is accidentally configured as an output.
相關(guān)PDF資料
PDF描述
A42MX24-1TQ100ES Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:25VA; Mounting Type:Chassis; External Depth:1.938"; External Height:2.313"; External Width:2.813"; Leaded Process Compatible:Yes
A42MX02-1TQ100I Power Transformer; Series:VPS; Power Rating:43VA; Mounting Type:Chassis; Current Rating:0.19 Series/0.38 Prllel A; External Depth:2.000"; External Height:2.688"; External Width:3.125"; Leaded Process Compatible:No RoHS Compliant: Yes
A42MX04-1TQ100I Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:80VA; Mounting Type:Chassis; Current Rating:0.35 Series/0.7 Prllel AA; External Depth:2.313"; External Height:3.000"; External Width:2.500"
A42MX09-1TQ100I XFRMR PWR 230.0VCT 0.57A QC .250
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1TQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ176 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA(27X27)
A42MX16-1TQ176I 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門陣列) 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA(27X27)
A42MX16-1TQ176M 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 176TQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 140 I/O 176TQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP