參數(shù)資料
型號(hào)： A42MX16-1TQ100ES
廠商： Electronic Theatre Controls, Inc.
英文描述： Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:20V; Power Rating:175VA; Mounting Type:Chassis RoHS Compliant: Yes
中文描述： 40MX和42MX FPGA系列
文件頁數(shù)： 30/120頁
文件大小： 854K
代理商： A42MX16-1TQ100ES
17
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.5.7
Reset and Interrupt Handling
The Atmel
AVR provides several different interrupt sources. These interrupts and the sepa-
rate Reset Vector each have a separate program vector in the program memory space. All
interrupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on
the Program Counter value, interrupts may be automatically disabled when Boot Lock bits
BLB02 or BLB12 are programmed. This feature improves software security. See Section
details.
The lowest addresses in the program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in Section 3.10 “Interrupts” on page 47.
The list also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 - the External Inter-
rupt Request 0. The Interrupt Vectors can be moved to the start of the Boot Flash section by
setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to Section 3.10 “Interrupts”
on page 47 for more information. The Reset Vector can also be moved to the start of the Boot
Flash section by programming the BOOTRST Fuse, see Section 3.19 “Boot Loader Support -
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled
interrupts can then interrupt the current interrupt routine. I-bit is automatically set when a Return
from Interrupt instruction - RETI - is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-
tor in order to execute the interrupt handling routine, and hardware clears the corresponding
Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)
to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is
cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is
cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt
Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the
Global Interrupt Enable bit is set, and will then be executed by order of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the
interrupt is enabled, the interrupt will not be triggered.
When the Atmel AVR exits from an interrupt, it will always return to the main program and exe-
cute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine, and
not restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.
No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the
CLI instruction. The following example shows how this can be used to avoid interrupts during the
timed EEPROM write sequence.
相關(guān)PDF資料
PDF描述
A42MX24-1TQ100ES Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:25VA; Mounting Type:Chassis; External Depth:1.938"; External Height:2.313"; External Width:2.813"; Leaded Process Compatible:Yes
A42MX02-1TQ100I Power Transformer; Series:VPS; Power Rating:43VA; Mounting Type:Chassis; Current Rating:0.19 Series/0.38 Prllel A; External Depth:2.000"; External Height:2.688"; External Width:3.125"; Leaded Process Compatible:No RoHS Compliant: Yes
A42MX04-1TQ100I Power Transformer; Series:VPS; Supply Voltage:115V; Output Voltage:222V; Power Rating:80VA; Mounting Type:Chassis; Current Rating:0.35 Series/0.7 Prllel AA; External Depth:2.313"; External Height:3.000"; External Width:2.500"
A42MX09-1TQ100I XFRMR PWR 230.0VCT 0.57A QC .250
A42MX02-1VQ100 XFRMR PWR 28.0VCT 4.6A QC .250
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A42MX16-1TQ100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ100M 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families
A42MX16-1TQ176 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1TQ176I 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27）
A42MX16-1TQ176M 制造商:Microsemi Corporation 功能描述:FPGA 24K GATES 608 CELLS 119MHZ/198MHZ 0.45UM 3.3V/5V 176TQF - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 140 I/O 176TQFP 制造商:Microsemi Corporation 功能描述:IC FPGA MX SGL CHIP 24K 176-TQFP
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*