- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4541 > A3PN020-1QNG68I (Microsemi SoC)IC FPGA NANO 20K GATES 68-QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | A3PN020-1QNG68I |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 11/114頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA NANO 20K GATES 68-QFN |
| 標(biāo)準(zhǔn)包裝： | 260 |
| 系列： | ProASIC3 nano |
| 輸入/輸出數(shù)： | 49 |
| 門數(shù)： | 20000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 68-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 68-QFN（8x8） |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)當(dāng)前第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
Datasheet Information
5-2
Revision 11
Revision 9
(continued)
The reference to guidelines for global spines and VersaTile rows, given in the "Global
Clock Contribution—PCLOCK" section, was corrected to t
he "Spine Architecture"
section of the Global Resources chapter in the IProASIC3 nano FPGA Fabric
Figure 2-3 has been modified for the DIN waveform; the Rise and Fall time label has
been changed to tDIN (37114).
The notes regarding drive strength in the "Summary of I/O Timing Characteristics –
tables were revised for clarification. They now state that the minimum drive strength
for the default software configuration when run in wide range is ±100 A. The drive
strength displayed in software is supported in normal range only. For a detailed I/V
curve, refer to the IBIS models (SAR 34759).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default I/O
Software Settings" section (SAR 34888).
Added values for minimum pulse width and removed the FRMAX row from Table 2-67
through Table 2-72 in the "Global Tree Timing Characteristics" section. Use the
software to determine the FRMAX for the device you are using (SAR 36956).
through
Table 2-73 ProASIC3 nano CCC/PLL Specification was updated. A note was added
indicating that when the CCC/PLL core is generated by Microsemi core generator
software, not all delay values of the specified delay increments are available (SAR
34823).
The port names in the SRAM "Timing Waveforms", SRAM "Timing Characteristics"
tables, Figure 2-34 FIFO Reset, and the FIFO "Timing Characteristics" tables were
revised to ensure consistency with the software names (SAR 35743).
Reference was made to a new application note, Simultaneous Read-Write Operations
in Dual-Port SRAM for Flash-Based cSoCs and FPGAs, which covers these cases in
detail (SAR 34871).
The "Pin Descriptions and Packaging" chapter has been added (SAR 34772).
July 2010
The versioning system for datasheets has been changed. Datasheets are assigned a
revision number that increments each time the datasheet is revised. The "ProASIC3
nano Device Status" table on page II indicates the status for each device in the device
family.
N/A
Revision 8
(April 2010)
References to differential inputs were removed from the datasheet, since ProASIC3
nano devices do not support differential inputs (SAR 21449).
N/A
The "ProASIC3 nano Device Status" table is new.
The JTAG DC voltage was revised in Table 2-2 Recommended Operating
Conditions 1, 2 (SAR 24052). The maximum value for VPUMP programming voltage
(operation mode) was changed from 3.45 V to 3.6 V (SAR 25220).
The highest temperature in Table 2-6 Temperature and Voltage Derating Factors for
Timing Delays was changed to 100C.
The typical value for A3PN010 was revised in Table 2-7 Quiescent Supply Current
Characteristics. The note was revised to remove the statement that values do not
include I/O static contribution.
Revision
Changes
Page
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3PN030-ZQNG48I | IC FPGA NANO 30K GATES 48-QFN |
| AGLN030V2-ZQNG68 | IC FPGA NANO 1KB 30K 68-QFN |
| BR24T02NUX-WTR | IC EEPROM I2C 2K 400KHZ 8-VSON |
| A3P030-2QNG68 | IC FPGA 1KB FLASH 30K 68-QFN |
| A3PN015-1QNG68I | IC FPGA NANO 15K GATES 68-QFN |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PN020-2QNG68 | 功能描述:IC FPGA NANO 20K GATES 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN020-2QNG68I | 功能描述:IC FPGA NANO 20K GATES 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN020-QNG68 | 功能描述:IC FPGA NANO 172MAC 68QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:60 系列:XP LAB/CLB數(shù):- 邏輯元件/單元數(shù):10000 RAM 位總計(jì):221184 輸入/輸出數(shù):244 門數(shù):- 電源電壓:1.71 V ~ 3.465 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:388-BBGA 供應(yīng)商設(shè)備封裝:388-FPBGA（23x23） 其它名稱:220-1241 |
| A3PN020-QNG68I | 功能描述:IC FPGA NANO 20K GATES 68-QFN RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PN030-VQG100 | 制造商:Microsemi Corporation 功能描述:FPGA PROASIC3 NANO 30K GATES 130NM 1.5V - Trays |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。