Revision 11 2-63 Timing Characteristics Table 2-74 RAM4K9 Commercial-Case Conditions: T<" />
參數(shù)資料
型號(hào): A3PN015-1QNG68I
廠商: Microsemi SoC
文件頁數(shù): 90/114頁
文件大?。?/td> 0K
描述: IC FPGA NANO 15K GATES 68-QFN
標(biāo)準(zhǔn)包裝: 260
系列: ProASIC3 nano
輸入/輸出數(shù): 49
門數(shù): 15000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 85°C
封裝/外殼: 68-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 68-QFN(8x8)
ProASIC3 nano Flash FPGAs
Revision 11
2-63
Timing Characteristics
Table 2-74 RAM4K9
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tAS
Address Setup time
0.25
0.28
0.33
ns
tAH
Address Hold time
0.00
ns
tENS
REN, WEN Setup time
0.14
0.16
0.19
ns
tENH
REN, WEN Hold time
0.10
0.11
0.13
ns
tBKS
BLK Setup time
0.23
0.27
0.31
ns
tBKH
BLK Hold time
0.02
ns
tDS
Input data (DIN) Setup time
0.18
0.21
0.25
ns
tDH
Input data (DIN) Hold time
0.00
ns
tCKQ1
Clock High to New Data Valid on DOUT (output retained, WMODE = 0)
1.79
2.03
2.39
ns
Clock High to New Data Valid on DOUT (flow-through, WMODE = 1)
2.36
2.68
3.15
ns
tCKQ2
Clock High to New Data Valid on DOUT (pipelined)
0.89
1.02
1.20
ns
tC2CWWL1 Address collision clk-to-clk delay for reliable write after write on same
address; applicable to closing edge
0.33
0.28
0.25
ns
tC2CWWH1 Address collision clk-to-clk delay for reliable write after write on same
address; applicable to rising edge
0.30
0.26
0.23
ns
tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same
address; applicable to opening edge
0.45
0.38
0.34
ns
tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same
address; applicable to opening edge
0.49
0.42
0.37
ns
tRSTBQ
RESET Low to Data Out Low on DOUT (flow through)
0.92
1.05
1.23
ns
RESET Low to Data Out Low on DOUT (pipelined)
0.92
1.05
1.23
ns
tREMRSTB
RESET Removal
0.29
0.33
0.38
ns
tRECRSTB
RESET Recovery
1.50
1.71
2.01
ns
tMPWRSTB RESET Minimum Pulse Width
0.21
0.24
0.29
ns
tCYC
Clock Cycle time
3.23
3.68
4.32
ns
FMAX
Maximum Frequency
310
272
231
MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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