Revision 13 2-69 Clock Conditioning Circuits CCC Electrical Specifications Timing Characteristics Ta" />
參數(shù)資料
型號： A3PE600-FGG484
廠商： Microsemi SoC
文件頁數(shù)： 145/162頁
文件大小： 0K
描述： IC FPGA 600000 GATES 484-FBGA
標準包裝： 40
系列： ProASIC3E
RAM 位總計： 110592
輸入/輸出數(shù)： 270
門數(shù)： 600000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 484-BGA
供應商設(shè)備封裝： 484-FPBGA（23x23）
ProASIC3E Flash Family FPGAs
Revision 13
2-69
Clock Conditioning Circuits
CCC Electrical Specifications
Timing Characteristics
Table 2-98 ProASIC3E CCC/PLL Specification
Parameter
Minimum
Typical
Maximum
Units
Clock Conditioning Circuitry Input Frequency fIN_CCC
1.5
350
MHz
Clock Conditioning Circuitry Output Frequency fOUT_CCC
0.75
350
MHz
Delay Increments in Programmable Delay Blocks 1, 2
1603
ps
Serial Clock (SCLK) for Dynamic PLL4
125
MHz
Number of Programmable Values in Each
Programmable Delay Block
32
Input Period Jitter
1.5
ns
CCC Output Peak-to-Peak Period Jitter FCCC_OUT
Max Peak-to-Peak Period Jitter
1 Global
Network Used
3 Global
Networks Used
0.75 MHz to 24 MHz
0.50%
0.70%
24 MHz to 100 MHz
1.00%
1.20%
100 MHz to 250 MHz
1.75%
2.00%
250 MHz to 350 MHz
2.50%
5.60%
Acquisition Time
LockControl = 0
300
s
LockControl = 1
6.0
ms
Tracking Jitter 5
LockControl = 0
1.6
ns
LockControl = 1
0.8
ns
Output Duty Cycle
48.5
51.5
%
Delay Range in Block: Programmable Delay 1 1, 2
0.6
5.56
ns
Delay Range in Block: Programmable Delay 2 1,2
0.025
5.56
ns
Delay Range in Block: Fixed Delay1,4
2.2
ns
Notes:
1. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings
2. TJ = 25°C, VCC = 1.5 V.
3. When the CCC/PLL core is generated by Microsemi core generator software, not all delay values of the specified delay
increments are available. Refer to the Libero SoC Online Help for more information.
4. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific junction
temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
5. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL input clock
edge. Tracking jitter does not measure the variation in PLL output period, which is covered by the period jitter
parameter.
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相關(guān)代理商/技術(shù)參數(shù)
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A3PE600-FGG484I 功能描述:IC FPGA 600000 GATES 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3E 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設(shè)備封裝:484-FPBGA（27X27）
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