2-54 Revision 13 Fully Registered I/O Buffers with Synchronous Enable and Asynchronous Clear<" />
參數(shù)資料
型號: A3PE600-FGG484
廠商: Microsemi SoC
文件頁數(shù): 128/162頁
文件大?。?/td> 0K
描述: IC FPGA 600000 GATES 484-FBGA
標(biāo)準(zhǔn)包裝: 40
系列: ProASIC3E
RAM 位總計: 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應(yīng)商設(shè)備封裝: 484-FPBGA(23x23)
ProASIC3E DC and Switching Characteristics
2-54
Revision 13
Fully Registered I/O Buffers with Synchronous Enable and
Asynchronous Clear
Figure 2-26 Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear
Enable
CLK
Pad
Out
CLK
Enable
CLR
Data_out
Data
Y
AA
EOUT
DOUT
Core
Array
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
DQ
DFN1E1C1
E
CLR
D_Enable
BB
CC
DD
EE
FF
GG
LL
HH
JJ
KK
CLKBUF
INBUF
TRIBUF
INBUF
CLKBUF
INBUF
Data Input I/O Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
Data Output Register and
Enable Output Register with
Active High Enable
Active High Clear
Positive-Edge Triggered
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