Revision 13 5-5 Revision 3 (Apr 2008) Packaging v1.2 The following pins had duplicates and the extra pins were delete" />
參數(shù)資料
型號: A3PE600-1FGG484
廠商: Microsemi SoC
文件頁數(shù): 63/162頁
文件大?。?/td> 0K
描述: IC FPGA 600000 GATES 484-FBGA
標準包裝: 40
系列: ProASIC3E
RAM 位總計: 110592
輸入/輸出數(shù): 270
門數(shù): 600000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 484-BGA
供應商設備封裝: 484-FPBGA(23x23)
ProASIC3E Flash Family FPGAs
Revision 13
5-5
Revision 3 (Apr 2008)
Packaging v1.2
The following pins had duplicates and the extra pins were deleted from the
"PQ208" A3PE3000 table:
36, 62, 171
Note: There were no pin function changes in this update.
The following pins had duplicates and the extra pins were deleted from the
"FG324" table:
E2, E3, E16, E17, P2, P3, T16, U17
Note: There were no pin function changes in this update.
The "FG256" pin table was updated for the A3PE600 device because the old PAT
were based on the IFX die, and this is the final UMC die version.
The "FG484" was updated for the A3PE600 device because the old PAT were
based on the IFX die, and this is the final UMC die version.
The following pins had duplicates and the extra pins were deleted from the
"FG896" table:
AD6, AE5, AE28, AF29, F5, F26, G6, G25
Note: There were no pin function changes in this update.
Revision 2 (Mar 2008)
Product Brief rev. 1
The FG324 package was added to the "ProASIC3E Product Family" table, the
A3PE3000.
I, II, IV
Revision 1 (Feb 2008)
DC
and
Switching
Characteristics v1.1
Temperature 1, Maximum Operating Junction Temperature was changed from
110°C to 100°C for both commercial and industrial grades.
In the "PLL Contribution—PPLL" section, the following was deleted:
FCLKIN is the input clock frequency.
was incorrect. It previously said TJ and it was corrected and changed to TA.
In Table 2-98 ProASIC3E CCC/PLL Specification, the SCLK parameter and note
1 are new.
Table 2-103 JTAG 1532 was populated with the parameter data, which was not
in the previous version of the document.
Revision 1 (cont’d)
Packaging v1.1
The "PQ208" pin table for A3PE3000 was updated.
The "FG324" pin table for A3PE3000 is new.
The "FG484" pin table for A3PE3000 is new.
The "FG896" pin table for A3PE3000 is new.
Revision 0 (Jan 2008) This document was previously in datasheet v2.1. As a result of moving to the
handbook format, Actel has restarted the version numbers. The new version
number is 51700098-001-0.
N/A
v2.1
(July 2007)
CoreMP7 information was removed from the "Features and Benefits" section.
i
The M1 device part numbers have been updated in Table 4 ProASIC3E
Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed
Grade and Temperature Grade Matrix", and "Speed Grade and Temperature
Grade Matrix".
ii, iii,
iv, iv
Revision
Changes
Page
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相關代理商/技術參數(shù)
參數(shù)描述
A3PE600-1FGG484I 功能描述:IC FPGA 600000 GATES 484-FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場可編程門陣列) 系列:ProASIC3E 標準包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應商設備封裝:484-FPBGA(27X27)
A3PE600-1FGG896 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1FGG896ES 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1FGG896I 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs
A3PE600-1FGG896PP 制造商:ACTEL 制造商全稱:Actel Corporation 功能描述:ProASIC3E Flash Family FPGAs