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參數(shù)資料
| 型號： | A3PE1500-2FGG676I |
| 廠商： | Microsemi SoC |
| 文件頁數(shù)： | 61/162頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1KB FLASH 1.5M 676-FBGA |
| 標(biāo)準(zhǔn)包裝： | 40 |
| 系列： | ProASIC3E |
| RAM 位總計(jì)： | 276480 |
| 輸入/輸出數(shù)： | 444 |
| 門數(shù)： | 1500000 |
| 電源電壓： | 1.425 V ~ 1.575 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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ProASIC3E Flash Family FPGAs
Revision 13
5-3
Revision 10
(continued)
"TBD" for 3.3 V LVCMOS Wide Range in Table 2-19 I/O Output Buffer Maximum
Resistances1 and Table 2-21 I/O Short Currents IOSH/IOSL was replaced by
"Same as regular 3.3 V LVCMOS" (SAR 33853).
3.3 V LVCMOS Wide Range information was separated from regular 3.3 V
LVCMOS and placed into its own new section, "3.3 V LVCMOS Wide Range".
Values of IOSH and IOSL were added in Table 2-29 Minimum and Maximum DC
Input and Output Levels (SAR 33853).
The formulas in the table notes for Table 2-20 I/O Weak Pull-Up/Pull-Down
Resistances were corrected (SAR 34755).
The AC Loading figures in the "Single-Ended I/O Characteristics" section were
updated to match tables in the "Summary of I/O Timing Characteristics – Default
I/O Software Settings" section (SAR 34889).
The titles and subtitles for Table 2-31 3.3 V LVCMOS Wide Range High Slew
and Table 2-32 3.3 V LVCMOS Wide Range Low Slew were corrected (SAR
37227).
The following notes were removed from Table 2-78 LVDS Minimum and
Maximum DC Input and Output Levels (SAR 34812):
±5%
Differential input voltage = ±350 mV
Minimum pulse width High and Low values were added to the tables in the
"Global Tree Timing Characteristics" section. The maximum frequency for global
clock parameter was removed from these tables because a frequency on the
global is only an indication of what the global network can do. There are other
limiters such as the SRAM, I/Os, and PLL. SmartTime software should be used to
determine the design frequency (SAR 36957).
A note was added to Table 2-98 ProASIC3E CCC/PLL Specification indicating
that when the CCC/PLL core is generated by Microsemi core generator software,
not all delay values of the specified delay increments are available (SAR 34824).
The following figures were deleted. Reference was made to a new application
cSoCs and FPGAs, which covers these cases in detail (SAR 34872).
Figure 2-44 Write Access after Write onto Same Address
Figure 2-45 Read Access after Write onto Same Address
Figure 2-46 Write Access after Read onto Same Address
The port names in the SRAM "Timing Waveforms", SRAM "Timing
Characteristics" tables were revised to ensure consistency with the software
names (SAR 35750).
The "Pin Descriptions and Packaging" chapter is new (SAR 34771).
Package names used in the "Package Pin Assignments" section were revised to
match standards given in Package Mechanical Drawings (SAR 34771).
Pin E6 for the FG256 package was corrected from VvB0 to VCCIB0 (SARs
30364, 31597, 26243).
July 2010
The versioning system for datasheets has been changed. Datasheets are
assigned a revision number that increments each time the datasheet is revised.
The "ProASIC3E Device Status" table on page II indicates the status for each
device in the device family.
N/A
Revision
Changes
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