ProASIC3L Low Power Flash FPGAs
Revision 13
2-59
Table 2-79 2.5 V LVCMOS Low Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/Os
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
4 mA
Std.
0.70
5.27
0.05
1.17
0.50
5.37
4.68
2.03
1.79
7.38
6.69
ns
–1
0.60
4.49
0.04
0.99
0.43
4.57
3.98
1.73
1.52
6.28
5.69
ns
6 mA
Std.
0.70
4.32
0.05
1.17
0.50
4.40
4.03
2.33
2.35
6.42
6.04
ns
–1
0.60
3.68
0.04
0.99
0.43
3.75
3.43
1.98
2.00
5.46
5.14
ns
8 mA
Std.
0.70
4.32
0.05
1.17
0.50
4.40
4.03
2.33
2.35
6.42
6.04
ns
–1
0.60
3.68
0.04
0.99
0.43
3.75
3.43
1.98
2.00
5.46
5.14
ns
12 mA
Std.
0.70
3.66
0.05
1.17
0.50
3.73
3.56
2.54
2.71
5.74
5.57
ns
–1
0.60
3.12
0.04
0.99
0.43
3.17
3.03
2.16
2.30
4.89
4.74
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values. Table 2-80 2.5 V LVCMOS High Slew – Applies to 1.2 V DC Core Voltage
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.14 V, Worst-Case VCCI = 2.3 V
Applicable to Standard Plus I/Os
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
4 mA
Std.
0.70
2.60
0.05
1.17
0.50
2.65
2.39
2.03
1.87
4.66
4.40
ns
–1
0.60
2.21
0.04
0.99
0.43
2.25
2.03
1.72
1.59
3.96
3.74
ns
6 mA
Std.
0.70
2.10
0.05
1.17
0.50
2.14
1.83
2.33
2.44
4.16
3.84
ns
–1
0.60
1.79
0.04
0.99
0.43
1.82
1.56
1.98
2.07
3.54
3.27
ns
8 mA
Std.
0.70
2.10
0.05
1.17
0.50
2.14
1.83
2.33
2.44
4.16
3.84
ns
–1
0.60
1.79
0.04
0.99
0.43
1.82
1.56
1.98
2.07
3.54
3.27
ns
12 mA
Std.
0.70
1.86
0.05
1.17
0.50
1.90
1.55
2.54
2.80
3.91
3.57
ns
–1
0.60
1.59
0.04
0.99
0.43
1.61
1.32
2.16
2.38
3.33
3.03
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-7 for derating values.