ProASIC3 Flash Family FPGAs
Revision 13
2-35
Table 2-43 3.3 V LVTTL / 3.3 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V
Applicable to Standard Plus I/O Banks
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tEOUT
tZL
tZH
tLZ
tHZ
tZLS
tZHS
Units
4 mA
Std.
0.66
7.20
0.04
1.00
0.43
7.34
6.29
2.27
2.34
9.57
8.52
ns
–1
0.56
6.13
0.04
0.85
0.36
6.24
5.35
1.93
1.99
8.14
7.25
ns
–2
0.49
5.38
0.03
0.75
0.32
5.48
4.69
1.70
1.75
7.15
6.36
ns
6 mA
Std.
0.66
4.50
0.04
1.00
0.43
4.58
3.82
2.58
2.88
6.82
6.05
ns
–1
0.56
3.83
0.04
0.85
0.36
3.90
3.25
2.19
2.45
5.80
5.15
ns
–2
0.49
3.36
0.03
0.75
0.32
3.42
2.85
1.92
2.15
5.09
4.52
ns
8 mA
Std.
0.66
4.50
0.04
1.00
0.43
4.58
3.82
2.58
2.88
6.82
6.05
ns
–1
0.56
3.83
0.04
0.85
0.36
3.90
3.25
2.19
2.45
5.80
5.15
ns
–2
0.49
3.36
0.03
0.75
0.32
3.42
2.85
1.92
2.15
5.09
4.52
ns
12 mA
Std.
0.66
3.16
0.04
1.00
0.43
3.22
2.58
2.79
3.22
5.45
4.82
ns
–1
0.56
2.69
0.04
0.85
0.36
2.74
2.20
2.37
2.74
4.64
4.10
ns
–2
0.49
2.36
0.03
0.75
0.32
2.40
1.93
2.08
2.41
4.07
3.60
ns
16 mA
Std.
0.66
3.16
0.04
1.00
0.43
3.22
2.58
2.79
3.22
5.45
4.82
ns
–1
0.56
2.69
0.04
0.85
0.36
2.74
2.20
2.37
2.74
4.64
4.10
ns
–2
0.49
2.36
0.03
0.75
0.32
2.40
1.93
2.08
2.41
4.07
3.60
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-6 for derating values.