參數(shù)資料
型號(hào): A3P125-VQ100II
元件分類(lèi): FPGA
英文描述: FPGA, 3072 CLBS, 125000 GATES, 350 MHz, PQFP100
封裝: 14 X 14 MM, 1 MM HEIGHT, 0.50 MM PITCH, VQFP-100
文件頁(yè)數(shù): 44/49頁(yè)
文件大?。?/td> 5893K
代理商: A3P125-VQ100II
ProASIC3 DC and Switching Characteristics
2- 78
v1.3
Global Resource Characteristics
A3P250 Clock Tree Topology
Clock delays are device-specific. Figure 2-27 is an example of a global tree used for clock routing.
The global tree presented in Figure 2-27 is driven by a CCC located on the west side of the A3P250
device. It is used to drive all D-flip-flops in the device.
Figure 2-27 Example of Global Tree Use in an A3P250 Device for Clock Routing
Central
Global Rib
VersaTile
Rows
Global Spine
CCC
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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