參數(shù)資料
型號: A32400DX-PQ240I
元件分類: FPGA
英文描述: FPGA, 2526 CLBS, 40000 GATES, PQFP240
封裝: PLASTIC, QFP-240
文件頁數(shù): 3/22頁
文件大?。?/td> 217K
代理商: A32400DX-PQ240I
11
3200DX Field Programmable Gate Arrays – The System Logic Integrator Family
Package Thermal Characteristics
The device junction to case thermal characteristic is
θjc, and
the junction to ambient air characteristic is
θja. The thermal
characteristics for
θja are shown with two different air flow
rates.
Maximum junction temperature is 150
°C.
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
commercial temperature is as follows:
Package Type
Pin Count
θja
Maximum Power Dissipation
Still Air
300 ft/min
Still Air
300 ft/min
Plastic Quad Flatpack
160
36
°C/W
30
°C/W
2.2 W
2.6 W
Plastic Quad Flatpack
208
25
°C/W
16.2
°C/W
3.2 W
4.9 W
Plastic Leaded Chip Carrier
84
37
°C/W
28
°C/W
2.2 W
2.9 W
Thin Quad Flatpack
176
32
°C/W
25
°C/W
2.5 W
3.2 W
Max. junction temp. (
°C) – Max. commercial temp.
θja (°C/W)
-----------------------------------------------------------------------------------------------------------------------------
150
°C – 70°C
30
°C/W
---------------------------------
2.6W
==
General Power Equation
P = [ICCstandby + ICCactive] * VCC + IOL* VOL* N
+ IOH * (VCC – VOH) * M
Where:
ICCstandby is the current flowing when no inputs or
outputs are changing.
ICCactive is the current flowing due to CMOS
switching.
IOL, IOH are TTL sink/source currents.
VOL, VOH are TTL level output voltages.
N equals the number of outputs driving TTL loads to
VOL.
M equals the number of outputs driving TTL loads to
VOH.
An accurate determination of N and M is problematic
because their values depend on the family type, design
details, and on the system I/O. The power can be divided into
two components: static and active.
Static Power Component
Actel FPGAs have small static power components that
result in lower power dissipation than PALs or PLDs. By
integrating multiple PALs/PLDs into one FPGA, an even
greater reduction in board-level power dissipation can
be achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for commercial, worst case conditions.
ICC
VCC
Power
2 mA
5.25 V
10.5 mW
The static power dissipation by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this number is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with
all outputs driving low and 140 mW with all outputs driving
high. The actual dissipation will average somewhere between
as I/Os switch states with time.
Active Power Component
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the external
I/O. Active power dissipation results from charging internal
chip capacitances of the interconnect, unprogrammed
antifuses, module inputs, and module outputs, plus external
capacitance due to PC board traces and load device inputs.
An additional component of the active power dissipation is
the totem-pole current in the CMOS transistor pairs. The net
effect can be associated with an equivalent capacitance that
can be combined with frequency and voltage to represent
active power dissipation.
相關(guān)PDF資料
PDF描述
A32400DX-FRQ240I FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-FRQ240M FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-RQ240B FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-RQ240C FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-RQ240I FPGA, 5020 CLBS, 40000 GATES, PQFP240
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