參數(shù)資料
型號(hào): A32400DX-PQ240I
元件分類: FPGA
英文描述: FPGA, 2526 CLBS, 40000 GATES, PQFP240
封裝: PLASTIC, QFP-240
文件頁數(shù): 17/22頁
文件大?。?/td> 217K
代理商: A32400DX-PQ240I
4
Logic Modules
The 3200DX contains three types of logic modules:
combinatorial (C-modules), sequential (S-modules), and
decode (D-modules). Both the C-module and S-module are
identical to the 1200XL family logic modules.
The combinatorial module (shown in Figure 1) implements
the following function:
Y=!S1*!S0*D00+!S1*S0*D01*S1*!S0*D01+S1*S0*D11
where:
S0=A0*B0
S1=A1 + B1
The S-module is designed to implement high-speed flip-flop
functions within a single module. The S-module implements
the same logic function as the C-module followed by a
sequential block. The sequential block can implement either a
D flip-flop or a transparent latch. The S-module can also be
configured as fully transparent so that it can be used to
implement purely combinatorial logic. The function of the
sequential module is determined by the macro selection from
the design library. The available S-module implementations
are shown in Figure 2.
D-modules are arranged around the periphery of the device
and contain wide decode circuits providing a fast decode
function similar to CPLDs and PALs (Figure 3). This is
Figure 1 C-module Implementation
D00
D10
D11
S0
S1
Y
A0
B0
A1
B1
Figure 2 S-module Implementations
D11
D01
D00
D10
Y
OUT
S1
S0
Up to 7-input function plus D-type ip-op with clear
D11
D01
D00
D10
Y
S1
S0
Up to 7-input function plus latch
Y
Up to 4-input function plus latch with clear
D11
D01
D00
D10
Y
OUT
S1
S0
Up to 8-input function (same as C-module)
S
D1
D0
CLR
DQ
OUT
CLR
DQ
OUT
GATE
DQ
GATE
相關(guān)PDF資料
PDF描述
A32400DX-FRQ240I FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-FRQ240M FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-RQ240B FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-RQ240C FPGA, 5020 CLBS, 40000 GATES, PQFP240
A32400DX-RQ240I FPGA, 5020 CLBS, 40000 GATES, PQFP240
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