參數(shù)資料
型號(hào)： A1440A-PQ160I
廠商： Microsemi SoC
文件頁(yè)數(shù)： 5/90頁(yè)
文件大小： 0K
描述： IC FPGA 4K GATES 160-PQFP
產(chǎn)品變化通告： A1440A Family Discontinuation 24/Jan/2012
標(biāo)準(zhǔn)包裝： 24
系列： ACT™ 3
LAB/CLB數(shù)： 564
輸入/輸出數(shù)： 131
門(mén)數(shù)： 4000
電源電壓： 4.5 V ~ 5.5 V
安裝類(lèi)型： 表面貼裝
工作溫度： -40°C ~ 85°C
封裝/外殼： 160-BQFP
供應(yīng)商設(shè)備封裝： 160-PQFP（28x28）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -5
Dedicated Clocks
Dedicated clock networks support high performance by providing sub-nanosecond skew and guaranteed
performance. Dedicated clock networks contain no programming elements in the path from the I/O Pad
Driver to the input of S-modules or I/O modules. There are two dedicated clock networks: one for the
array registers (HCLK), and one for the I/O registers (IOCLK). The clock networks are accessed by
special I/Os.
The routed clock networks are referred to as CLK0 and CLK1. Each network is connected to a clock
module (CLKMOD) that selects the source of the clock signal and may be driven as follows (Figure 2-6):
Externally from the CLKA pad
Externally from the CLKB pad
Internally from the CLKINA input
Internally from the CLKINB input
The clock modules are located in the top row of I/O modules. Clock drivers and a dedicated horizontal
clock track are located in each horizontal routing channel. The function of the clock module is determined
by the selection of clock macros from the macro library. The macro CLKBUF is used to connect one of
the two external clock pins to a clock network, and the macro CLKINT is used to connect an internally
generated clock signal to a clock network. Since both clock networks are identical, the user does not care
whether CLK0 or CLK1 is being used. Routed clocks can also be used to drive high fanout nets like
resets, output enables, or data enables. This saves logic modules and results in performance increases
in some cases.
Routing Structure
The ACT 3 architecture uses vertical and horizontal routing tracks to connect the various logic and I/O
modules. These routing tracks are metal interconnects that may either be of continuous length or broken
into segments. Segments can be joined together at the ends using antifuses to increase their lengths up
to the full length of the track.
Figure 2-6
Clock Networks
CLKB
CLKA
FROM
PADS
CLOCK
DRIVERS
CLKMOD
CLKINB
CLKINA
S0
S1
INTERNAL
SIGNAL
CLKO(17)
CLKO(16)
CLKO(15)
CLKO(2)
CLKO(1)
CLOCK TRACKS
相關(guān)PDF資料
PDF描述
A14V40A-PQ160C IC FPGA 4K GATES 3.3V 160-PQFP
AYM43DTMS-S189 CONN EDGECARD 86POS R/A .156 SLD
XC3030A-7PC44C IC LOGIC CL ARRAY 3000GAT 44PLCC
XC3020A-7PC84C IC LOGIC CL ARRAY 2000GAT 84PLCC
ASM43DTMS-S189 CONN EDGECARD 86POS R/A .156 SLD
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1440A-PQG160C 功能描述:IC FPGA 4K GATES 160-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
A1440A-PQG160I 功能描述:IC FPGA 4K GATES 160-PQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
A1440ASTDPQ175C 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:ASIC
A1440A-TQ176C 功能描述:IC FPGA 4K GATES 176-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
A1440A-TQ176I 功能描述:IC FPGA 4K GATES 176-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ACT™ 3 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
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