參數(shù)資料
型號(hào)： A1425A-2PQG100I
元件分類(lèi)： FPGA
英文描述： FPGA, 310 CLBS, 2500 GATES, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 1/68頁(yè)
文件大?。?/td> 489K
代理商： A1425A-2PQG100I
September 1997
1-175
1997 Actel Corporation
Accelerator Series FPGAs
– ACT 3 Family
Features
Up to 10,000 Gate Array Equivalent Gates
(up to 25,000 equivalent PLD Gates)
Highly Predictable Performance with 100% Automatic
Placement and Routing
7.5 ns Clock-to-Output Times
Up to 250 MHz On-Chip Performance
Up to 228 User-Programmable I/O Pins
Four Fast, Low-Skew Clock Networks
More than 500 Macro Functions
Replaces up to twenty 32 macro-cell CPLDs
Replaces up to one hundred 20-pin PAL Packages
Up to 1153 Dedicated Flip-Flops
VQFP, TQFP, BGA, and PQFP Packages
Nonvolatile, User Programmable
Fully Tested Prior to Shipment
5.0V and 3.3V Versions
Optimized for Logic Synthesis Methodologies
Low-power CMOS Technology
Device
A1415
A1425
A1440
A1460
A14100
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages (40 gates)
20-Pin PAL Equivalent Packages (100 gates)
1,500
3,750
40
15
2,500
6,250
60
25
4,000
10,000
100
40
6,000
15,000
150
60
10,000
25,000
250
100
Logic Modules
S-Module
C-Module
200
104
96
310
160
150
564
288
276
848
432
416
1,377
697
680
Dedicated Flip-Flops1
264
360
568
768
1,153
User I/Os (maximum)
80
100
140
168
228
Packages2 (by pin count)
CPGA
PLCC
PQFP
RQFP
VQFP
TQFP
BGA
CQFP
100
84
100
—
100
—
133
84
100, 160
—
100
—
132
175
84
160
—
100
176
—
207
—
160, 208
—
176
225
196
257
—
208
—
313
256
Performance3 (maximum, worst-case commercial)
Chip-to-Chip4
Accumulators (16-bit)
Loadable Counter (16-bit)
Prescaled Loadable Counters (16-bit)
Datapath, Shift Registers
Clock-to-Output (pad-to-pad)
108 MHz
63 MHz
110 MHz
250 MHz
7.5 ns
108 MHz
63 MHz
110 MHz
250 MHz
7.5 ns
100 MHz
63 MHz
110 MHz
250 MHz
8.5 ns
97 MHz
63 MHz
110 MHz
200 MHz
9.0 ns
93 MHz
63 MHz
105 MHz
200 MHz
9.5 ns
Notes:
1.
One flip-flop per S-Module, two flip-flops per I/O-Module.
2.
See product plan on page 1-178 for package availability.
3.
Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.
4.
Clock-to-Output + Setup
相關(guān)PDF資料
PDF描述
A1425A-2PQG160C FPGA, 310 CLBS, 2500 GATES, 200 MHz, PQFP160
A1425A-2PQG160I FPGA, 310 CLBS, 2500 GATES, PQFP160
A1425A-2VQG100C FPGA, 310 CLBS, 2500 GATES, 200 MHz, PQFP100
A1425A-2VQG100I FPGA, 310 CLBS, 2500 GATES, PQFP100
A1425A-PLG84C FPGA, 310 CLBS, 2500 GATES, 125 MHz, PQCC84
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1425A-2PQG160C 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 160PQFP - Trays
A1425A-2PQG160I 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 160PQFP - Trays
A1425A-2VQ100C 制造商:Microsemi SOC Products Group 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 100VQFP - Trays
A1425A-2VQ100I 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 100VQFP - Trays
A1425A-2VQG100C 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 2.5K GATES 310 CELLS 200MHZ 0.8UM 5V 100VQFP - Trays
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