參數(shù)資料
型號(hào)： A1415A-VQG100C
廠商： Microsemi SoC
文件頁(yè)數(shù)： 3/90頁(yè)
文件大?。?/td> 0K
描述： IC FPGA 1500 GATES 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： ACT™ 3
LAB/CLB數(shù)： 200
輸入/輸出數(shù)： 80
門數(shù)： 1500
電源電壓： 4.5 V ~ 5.5 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
Accelerator Series FPGAs – ACT 3 Family
R e visio n 3
2 -3
The S-module contains a full implementation of the C-module plus a clearable sequential element that
can either implement a latch or flip-flop function. The S-module can therefore implement any function
implemented by the C-module. This allows complex combinatorial-sequential functions to be
implemented with no delay penalty. The Designer Series Development System will automatically
combine any C-module macro driving an S-module macro into the S-module, thereby freeing up a logic
module and eliminating a module delay.
The clear input CLR is accessible from the routing channel. In addition, the clock input may be connected
to one of three clock networks: CLKA, CLKB, or HCLK. The C-module and S-module functional
descriptions are shown in Figure 2-2 and Figure 2-3 on page 2-2. The clock selection is determined by a
multiplexer select at the clock input to the S-module.
I/Os
I/O Modules
I/O modules provide an interface between the array and the I/O Pad Drivers. I/O modules are located in
the array and access the routing channels in a similar fashion to logic modules. The I/O module
schematic is shown in Figure 4. The signals DataIn and DataOut connect to the I/O pad driver.
Each I/O module contains two D-type flip-flops. Each flip-flop is connected to the dedicated I/O clock
(IOCLK). Each flip-flop can be bypassed by nonsequential I/Os. In addition, each flip-flop contains a data
enable input that can be accessed from the routing channels (ODE and IDE). The asynchronous
preset/clear input is driven by the dedicated preset/clear network (IOPCL). Either preset or clear can be
selected individually on an I/O module by I/O module basis.
Figure 2-4
Functional Diagram for I/O Module
D
DATAOUT
D
Q
CLR/PRE
DATAIN
IOCLK
IOPCL
Y
D
Q
CLR/PRE
ODE
MUX
1
0
MUX
1
0
MUX
0
1
MUX
3
0
1
2
S1
S0
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A1415A-VQG100I 功能描述:IC FPGA 1500 GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ACT™ 3 產(chǎn)品培訓(xùn)模塊:Three Reasons to Use FPGA's in Industrial Designs Cyclone IV FPGA Family Overview 特色產(chǎn)品:Cyclone? IV FPGAs 標(biāo)準(zhǔn)包裝:60 系列:CYCLONE® IV GX LAB/CLB數(shù):9360 邏輯元件/單元數(shù):149760 RAM 位總計(jì):6635520 輸入/輸出數(shù):270 門數(shù):- 電源電壓:1.16 V ~ 1.24 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FBGA（23x23）
A1415A-VQG100M 制造商:Microsemi Corporation 功能描述:FPGA ACT 3 1.5K GATES 200 CELLS 125MHZ 0.8UM 5V 100VQFP - Trays 制造商:Microsemi Corporation 功能描述:IC FPGA 80 I/O 100VQFP
A14162-02 功能描述:導(dǎo)熱接口產(chǎn)品 Tflex 280V0 18x18" 1.1W/mK RoHS:否 制造商:Panasonic Electronic Components 類型:Thermal Graphite Sheets 材料:Graphite Polymer Film 長(zhǎng)度:180 mm 寬度:115 mm 厚度:0.07 mm 工作溫度范圍:
A14162-06 功能描述:導(dǎo)熱接口產(chǎn)品 Tflex 280V0 9x9" 1.1W/mK RoHS:否 制造商:Panasonic Electronic Components 類型:Thermal Graphite Sheets 材料:Graphite Polymer Film 長(zhǎng)度:180 mm 寬度:115 mm 厚度:0.07 mm 工作溫度范圍:
A14162-11 功能描述:導(dǎo)熱接口產(chǎn)品 Tflex 260V0 9x9" 1.1W/mK RoHS:否 制造商:Panasonic Electronic Components 類型:Thermal Graphite Sheets 材料:Graphite Polymer Film 長(zhǎng)度:180 mm 寬度:115 mm 厚度:0.07 mm 工作溫度范圍:
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