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參數資料
| 型號： | A1181 |
| 廠商： | Allegro MicroSystems, Inc. |
| 英文描述： | Two-Wire, Programmable, Chopper-Stabilized, Unipolar Hall-Effect Switch |
| 中文描述： | 兩線，可編程，斬波穩(wěn)定，單極霍爾效應開關 |
| 文件頁數： | 5/16頁 |
| 文件大?。?/td> | 356K |
| 代理商： | A1181 |
13
A1180-DS, Rev. 2
Worcester, Massachusetts 01615-0036 (508) 853-5000
115 Northeast Cutoff, Box 15036
www.allegromicro.com
Allegro MicroSystems, Inc.
Sensitive Two-Wire Field-Programmable Chopper-Stabilized Unipolar Hall Effect Switches
A1180/81/82/83
The pulse sequences consist of the following groups of pulses:
1. An enable sequence.
2. A biteld address sequence.
3. When permanently setting the biteld, a long VPH fuse-blow-
ing pulse. (Note: Blown bit fuses cannot be reset.)
4. When permanently setting the biteld, the level of VCC must
be allowed to drop to zero between each pulse sequence, in
order to clear all registers. However, when provisionally set-
ting bitelds, VCC must be maintained at VPL between pulse
sequences, in order to maintain the prior biteld settings while
preparing to set additional bitelds.
Bitelds that are not set are evaluated as zeros. The biteld-level
fuses for 0 value bitelds are never blown. This prevents inad-
vertently setting the biteld to 1. Instead, blowing the device-
level fuse protects the 0 bitelds from being accidentally set in
the future.
When provisionally trying the calibration value, one pulse
sequence is used, using decimal values. The sequence for setting
the value 510 is shown in gure 5.
When permanently setting values, the bitelds must be set indi-
vidually, and 510 must be programmed as binary 101. Bit 3 is
set to 1 (0001002, which is 410), then bit 1 is set to 1 (0000012,
which is 110). Bit 2 is ignored, and so remains 0.Two pulse
sequences for permanently setting the calibration value 5 are
shown in gure 6. The nal VPH pulse is maintained for a longer
period, enough to blow the corresponding biteld-level fuse.
VPH
V+
t
VPM
VPL
0
Encode 001002 (410)
Enable
Address
Blow
Enable
Encode 000012 (110)
Figure 6. Pulse sequence to permanently encode calibration value 5 (101 binary, or
biteld address 3 and biteld address 1).
VPH
V+
t
VPM
VPL
0
Try 510
Enable
Address
Clear
Optional
Monitoring
Figure 5. Pulse sequence to provisionally try calibration value 5.
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