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參數(shù)資料
| 型號(hào)： | A1020B-PLG68C |
| 廠商： | Microsemi SoC |
| 文件頁(yè)數(shù)： | 89/98頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 2K GATES 68-PLCC COM |
| 標(biāo)準(zhǔn)包裝： | 19 |
| 系列： | ACT™ 1 |
| LAB/CLB數(shù)： | 547 |
| 輸入/輸出數(shù)： | 57 |
| 門數(shù)： | 2000 |
| 電源電壓： | 4.5 V ~ 5.5 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（24.23x24.23） |
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9
Hi R e l F P GA s
Ac t e l Ex t end ed Fl ow 1
Notes:
1.
Actel offers the extended flow for customers who require additional screening beyond the requirements of the MIL-STD-833, Class B. Actel is
compliant to the requirements of MIL-STD-883, Paragraph 1.2.1, and MIL-I-38535, Appendix A. Actel is offering this extended flow
incorporating the majority of the screening procedures as outlined in Method 5004 of MIL-STD-883, Class S. The exceptions to Method 5004
are shown in notes 2 and 3 below.
2.
Wafer lot acceptance is performed to Method 5007; however, the step coverage requirement as specified in Method 2018 must be waived.
3.
MIL-STD-883, Method 5004 requires 100 percent Radiation latch-up testing (Method 1020). Actel will not be performing any radiation testing,
and this requirement must be waived in its entirety.
Step
Screen
Method
Require-
ment
1.
Wafer Lot Acceptance2
5007 with Step Coverage Waiver
All Lots
2.
Destructive In-Line Bond Pull3
2011, Condition D
Sample
3.
Internal Visual
2010, Condition A
100%
4.
Serialization
100%
5.
Temperature Cycling
1010, Condition C
100%
6.
Constant Acceleration
2001, Condition D or E, Y1 Orientation Only
100%
7.
Particle Impact Noise Detection
2020, Condition A
100%
8.
Radiographic
2012 (one view only)
100%
9.
Pre-Burn-In Test
In accordance with applicable Actel device specification
100%
10.
Burn-in Test
1015, Condition D, 240 hours @ 125°C minimum
100%
11.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
12.
Reverse Bias Burn-In
1015, Condition C, 72 hours @ 150°C minimum
100%
13.
Interim (Post-Burn-In) Electrical Parameters
In accordance with applicable Actel device specification
100%
14.
Percent Defective Allowable (PDA)
Calculation
5%, 3% Functional Parameters @ 25°C
All Lots
15.
Final Electrical Test
a. Static Tests
(1) 25°C
(Subgroup 1, Table1)
(2) –55°C and +125°C
(Subgroups 2, 3, Table 1)
b. Functional Tests
(1) 25°C
(Subgroup 7, Table 15)
(2) –55°C and +125°C
(Subgroups 8A and B, Table 1)
c. Switching Tests at 25°C
(Subgroup 9, Table 1)
In accordance with Actel applicable device specification
which includes a, b, and c:
5005
100%
16.
Seal
a. Fine
b. Gross
1014
100%
17.
External Visual
2009
100%
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| A1020B-PLG68I | 功能描述:IC FPGA 2K GATES 68-PLCC IND RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:ACT™ 1 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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