A1 41 00 A Ti m i ng Cha r act e r i s t i cs (continued) (W or s" />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉锛� A1010B-VQ80C
寤犲晢锛� Microsemi SoC
鏂囦欢闋佹暩(sh霉)锛� 42/98闋�
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC FPGA 1200 GATES 80-VQFP COM
妯欐簴鍖呰锛� 90
绯诲垪锛� ACT™ 1
LAB/CLB鏁�(sh霉)锛� 295
杓稿叆/杓稿嚭鏁�(sh霉)锛� 57
闁€鏁�(sh霉)锛� 1200
闆绘簮闆诲锛� 4.5 V ~ 5.5 V
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
宸ヤ綔婧害锛� 0°C ~ 70°C
灏佽/澶栨锛� 80-TQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 80-VQFP锛�14x14锛�
47
Hi R e l F P GA s
A1 41 00 A Ti m i ng Cha r act e r i s t i cs (continued)
(W or s t - C as e M i l i t a r y Cond i t i o n s , V CC = 4.5 V, TJ = 1 25掳C)
鈥樷€�1鈥� Speed
鈥楽td鈥� Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Routed Array Clock Networks
tRCKH
Input Low to High (FO=256)
9.0
10.5
ns
tRCKL
Input High to Low (FO=256)
9.0
10.5
ns
tRPWH
Min. Pulse Width High (FO=256)
6.3
7.1
ns
tRPWL
Min. Pulse Width Low (FO=256)
6.3
7.1
ns
tRCKSW
Maximum Skew (FO=128)
1.9
2.1
ns
tRP
Minimum Period (FO=256)
12.9
14.5
ns
fRMAX
Maximum Frequency (FO=256)
75
65
MHz
Clock-to-Clock Skews
tIOHCKSW
I/O Clock to H-Clock Skew
0.0
3.5
0.0
3.5
ns
tIORCKSW
I/O Clock to R-Clock Skew
0.0
5.0
0.0
5.0
ns
tHRCKSW
H-Clock to R-Clock Skew
(FO = 64)
(FO = 50% max.)
0.0
1.0
3.0
0.0
1.0
3.0
ns
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
A1010B-VQG80C IC FPGA 1200 GATES 80-VQFP COM
M1AGL1000V5-FGG484 IC FPGA 1KB FLASH 1M 484-FBGA
M1AGL1000V5-FG484 IC FPGA 1KB FLASH 1M 484-FBGA
AGL1000V5-FG484 IC FPGA 1KB FLASH 1M 484FBGA
AFS600-FGG484 IC FPGA 4MB FLASH 600K 484FBGA
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉)
鍙冩暩(sh霉)鎻忚堪
A1010BVQ80I 鍒堕€犲晢:Microsemi SOC Products Group 鍔熻兘鎻忚堪:1010BVQ80I
A1010B-VQ80I 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP IND RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1010B-VQG80C 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP COM RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1010B-VQG80I 鍔熻兘鎻忚堪:IC FPGA 1200 GATES 80-VQFP IND RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 宓屽叆寮� - FPGA锛堢従(xi脿n)鍫村彲绶ㄧ▼闁€闄ｅ垪锛� 绯诲垪:ACT™ 1 妯欐簴鍖呰:40 绯诲垪:SX-A LAB/CLB鏁�(sh霉):6036 閭忚集鍏冧欢/鍠厓鏁�(sh霉):- RAM 浣嶇附瑷�:- 杓稿叆/杓稿嚭鏁�(sh霉):360 闁€鏁�(sh霉):108000 闆绘簮闆诲:2.25 V ~ 5.25 V 瀹夎椤炲瀷:琛ㄩ潰璨艰 宸ヤ綔婧害:0°C ~ 70°C 灏佽/澶栨:484-BGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:484-FPBGA锛�27X27锛�
A1010J1AQE2 鍒堕€犲晢:Switchcraft 鍔熻兘鎻忚堪:TOGGLE SWITCH
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