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參數(shù)資料
| 型號(hào)： | 9UMS9633BKLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 166.67 MHz, OTHER CLOCK GENERATOR, PQCC48 |
| 封裝： | 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48 |
| 文件頁(yè)數(shù)： | 5/22頁(yè) |
| 文件大?。?/td> | 208K |
| 代理商： | 9UMS9633BKLFT |
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IDTTM/ICSTM Ultra Mobile PC/Mobile Internet Device
1423—01/20/09
ICS9UMS9633B
ULTRA MOBILE PC/MOBILE INTERNET DEVICE
13
Advance Information
Byte
0
PLL & Divider Enable Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
-
PLL1 Enable
This bit controls whether the PLL driving the CPU
and SRC clocks is enabled or not.
RW
0 = Disabled
1 = Enabled
1
6
-
PLL2 Enable
This bit controls whether the PLL driving the DOT
and clock is enabled or not.
RW
0 = Disabled
1 = Enabled
1
5
-
PLL3 Enable
This bit controls whether the PLL driving the LCD
clock is enabled or not.
RW
0 = Disabled
1 = Enabled
1
4-
0
3
-
CPU Divider Enable
This bit controls whether the CPU output divider is
enabled or not.
NOTE: This bit should be automatically set to ‘0’ if
bit 7 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
2-
SRC Output Divider
Enable
This bit controls whether the SRC output divider is
enabled or not.
NOTE: This bit should be automatically set to ‘0’ if
bit 7 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
1-
LCD Output Divider
Enable
This bit controls whether the LCD output divider is
enabled or not.
NOTE: This bit should be automatically set to ‘0’ if
bit 5 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
0-
DOT Output Divider
Enable
This bit controls whether the DOT output divider is
enabled or not.
NOTE: This bit should be automatically set to ‘0’ if
bit 6 is set to ‘0’.
RW
0 = Disabled
1 = Enabled
1
Byte
1
PLL SS Enable/Control Register
Bit(s)
Pin #
Name
Description
Type
0
1
Default
7
PLL1 SS Enable
This bit controls whether PLL1 has spread enabled
or not. Spread spectrum for PLL1 is set at -0.5%
down-spread. Note that PLL1 drives the CPU and
SRC clocks.
RW
0 = Disabled
1 = Enabled
1
6
PLL3 SS Enable
This bit controls whether PLL3 has spread enabled
or not. Note that PLL3 drives the SSC clock, and
that the spread spectrum amount is set in bits 3-5.
RW
0 = Disabled
1 = Enabled
1
5
0
4
0
3
0
2
0
1
0
Reserved
See Table 2: LCD Spread
Select Table
PLL3 FS Select
These 3 bits select the frequency of PLL3 and the
SSC clock when Byte 1 Bit 6 (PLL3 Spread
Spectrum Enable) is set.
RW
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