參數(shù)資料
型號(hào)： 9S12DP512DGV1
英文描述： 9S12Dx512 Device Guide
中文描述： 9S12Dx512設(shè)備指南
文件頁數(shù)： 67/126頁
文件大?。?/td> 1809K
代理商： 9S12DP512DGV1
MC9S12DJ64 Device User Guide — V01.17
67
Section 4 Modes of Operation
4.1 Overview
Eight possible modes determine the operating configuration of the MC9S12DJ64. Each mode has an
associated default memory map and external bus configuration.
Three low power modes exist for the device.
4.2 Chip Configuration Summary
TheoperatingmodeoutofresetisdeterminedbythestatesoftheMODC,MODB,andMODApinsduring
reset(
Table 4-1
).TheMODC,MODB,andMODAbitsintheMODEregistershowthecurrentoperating
modeandprovidelimitedmodeswitchingduringoperation.ThestatesoftheMODC,MODB,andMODA
pinsarelatchedintothesebitsontherisingedgeoftheresetsignal.TheROMCTLsignalallowsthesetting
of the ROMON bit in the MISC register thus controlling whether the internal Flash is visible in the
memory map. ROMON = 1 mean the Flash is visible in the memory map. The state of the ROMCTL pin
is latched into the ROMON bit in the MISC register on the rising edge of the reset signal.
For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide.
Table 4-1 Mode Selection
BKGD =
MODC
PE6 =
MODB
PE5 =
MODA
PK7 =
ROMCTL
ROMON
Bit
Mode Description
0
0
0
X
1
Special Single Chip, BDM allowed and ACTIVE. BDM is
allowed in all other modes but a serial command is
required to make BDM active.
0
0
1
0
1
X
0
1
X
0
1
1
0
0
1
0
1
0
1
Emulation Expanded Narrow, BDM allowed
0
1
0
Special Test (Expanded Wide), BDM allowed
0
1
1
Emulation Expanded Wide, BDM allowed
1
0
0
Normal Single Chip, BDM allowed
1
0
1
Normal Expanded Narrow, BDM allowed
1
1
0
X
1
Peripheral; BDM allowed but bus operations would cause
bus conflicts (must not be used)
1
1
1
0
1
0
1
Normal Expanded Wide, BDM allowed
Table 4-2 Clock Selection Based on PE7
PE7 = XCLKS
1
Description
Colpitts Oscillator selected
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