參數(shù)資料
型號(hào)： 9LPRS436CKLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48
封裝： 6 X 6 MM, 0.40 MM PITCH, ROHS COMPLIANT, PLASTIC, MLF-48
文件頁數(shù)： 15/20頁
文件大小： 195K
代理商： 9LPRS436CKLFT
IDT
Low Power Clock for Intel Atom-Based Systems
1561C — 08/24/11
9LPRS436C
Low Power Clock for Intel Atom
-Based Systems
4
Pin Description (Continued)
25
GND
PWR
Ground pin.
26
VDDPCIEX
PWR
Power supply for PCI Express clocks, nominal 3.3V
27
CPUITPC_LR2/PCIeC_LR2
OUT
Complementary clock of differential pair CPU output. / Complementary clock of
differential PCIEX pair. These are 0.8V push pull outputs. No external 50ohm
resistor to GND or 33ohm series resistor needed.
28
CPUITPT_LR2/PCIeT_LR2
OUT
True clock of differential pair CPU output. / True clock of differential PCIEX
pair. These are 0.8V push pull outputs. No external 50ohm resistor to GND or
33ohm series resistor needed.
29
CPUC_LR1
OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor.
30
CPUT_LR1
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor.
31
VDDCPU
PWR
Supply for CPU clocks, 3.3V nominal
32
CPUC_LR0
OUT
Complementary clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor.
33
CPUT_LR0
OUT
True clock of differential pair 0.8V push-pull CPU outputs with integrated
33ohm series resistor.
34
GND
PWR
Ground pin.
35
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
36
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
37
CPU_STOP#
IN
Stops CPU0 clock when enabled.
38
PCI&PCIEX_STOP#
IN
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not
effected by this input.
39
X2_25
OUT
Crystal output, Nominally 25.00MHz.
40
X1_25
IN
Crystal input, Nominally 25.00MHz.
41
GND
PWR
Ground pin.
42
25MHz
OUT
25MHz clock output, 3.3V
43
VDDSUSP
PWR
Supply for suspend mode, powers 25MHz PLL, 25M output and XTAL
oscillator. 3.3V Nominal
44
Vtt_PwrGd/WOL_STOP#
IN
This active high 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled / Asynchronous active
low input pin that stops all outputs except free running 25Mhz
45
VDD14
PWR
Power for 14.31818MHz PLL and REF output, nominal 3.3V.
46
REF0_2x/FSLC
I/O
2x strength 14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency
selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values.
47
GND
PWR
Ground pin.
48
GND
PWR
Ground pin.
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9LPRS462AGLF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS462AGLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
9LPRS464AGLF 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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