參數(shù)資料
型號(hào)： 9LPR502YGLFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56
封裝： 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56
文件頁(yè)數(shù)： 29/29頁(yè)
文件大?。?/td> 282K
代理商： 9LPR502YGLFT
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator
1124D—02/26/09
Advance Information
ICS9LPR502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
9
Datasheet
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
29
GNDSRC
PWR
Ground pin for SRC clocks.
30
SRCT3/CR#_C
I/O
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 0
or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be
disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
31
SRCC3/CR#_D
I/O
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of SRC pair 1
or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output must first be
disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin can then be set to
serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit located in byte 5 of SMBUs
address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
32
VDDSRC_IO
PWR
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
33
SRCT4
I/O
True clock of differential SRC clock pair 4
34
SRCC4
I/O
Complement clock of differential SRC clock pair 4
35
SRCC11
OUT
Complement clock of low power differential SRC clock pair.
36
SRCT11
OUT
True clock of low power differential SRC clock pair.
37
CPU_STOP#/SRCC5
I/O
Stops all CPU Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6,
PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows:
0= CPU_STOP#
1 = SRC5
In AMT mode 3 bits are shifted in from the ICH to set the FSC, FSB, FSA values
38
PCI_STOP#/SRCT5
I/O
Stops all PCI Clocks, except those set to be free running clocks /
Complement clock of differential SRC pair. The function of this pin is set up by the power-up strap on pin 6,
PCI4/SRC5_EN. The logic value sampled on pin 6 at power-up sets the function as follows:
0= PCI_STOP#
1 = SRC5#
In AMT mode, this pin is a clock input which times the FSC, FSB, FSA bits shifted in on pin 37.
39
VDDSRC
PWR
VDD pin for SRC Pre-drivers, 3.3V nominal
40
GNDSRC
PWR
Ground for SRC clocks
41
SRCC7/CR#_E
I/O
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus.
Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of
SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
42
SRCT7/CR#_F
I/O
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus.
Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of
SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock
Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9LPR502YKLFT 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
9LPR515CGLF 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1
9LPR515CGLFT 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1,000
9LPR515CKLF 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1
9LPR515CKLFT 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購(gòu) 標(biāo)準(zhǔn)包裝:1,000
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