- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄25569 > 9LPR502YGLFT (INTEGRATED DEVICE TECHNOLOGY INC) SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 PDF資料下載
參數(shù)資料
| 型號： | 9LPR502YGLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO56 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-56 |
| 文件頁數(shù)： | 2/29頁 |
| 文件大?。?/td> | 282K |
| 代理商： | 9LPR502YGLFT |
第1頁當前第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
IDTTM/ICSTM
56-pin CK505 w/Fully Integrated Voltage Regulator
1124D—02/26/09
Advance Information
ICS9LPR502
56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR
10
Datasheet
MLF Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
43
VDDSRC_IO
PWR
Power supply for SRC outputs. 1.05 to 3.3V +/-5%.
44
CPUC2_ITP/SRCC8
OUT
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this
pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
45
CPUT2_ITP/SRCT8
OUT
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
46
NC
Not Connected
47
VDDCPU_IO
PWR
Power supply for CPU outputs. 1.05 to 3.3V +/-5%.
48
CPUC1_F
OUT
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
49
CPUT1_F
OUT
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
50
GNDCPU
PWR
Ground Pin for CPU Outputs
51
CPUC0
OUT
Complement clock of low power differential CPU clock pair.
52
CPUT0
OUT
True clock of low power differential CPU clock pair.
53
VDDCPU
PWR
Power Supply 3.3V nominal.
54
CK_PWRGD/PD#
IN
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
55
FSLB/TEST_MODE
IN
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS
values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer
to Test Clarification Table.
56
GNDREF
PWR
Ground pin for crystal oscillator circuit
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9LPRS365BKLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC64 |
| 9LPRS365BGLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO64 |
| 9LPRS436CKLF | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48 |
| 9LPRS436CGLF | SPECIALTY MICROPROCESSOR CIRCUIT, PDSO48 |
| 9LPRS436CKLFT | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9LPR502YKLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:56-PIN CK505 W/FULLY INTEGRATED VOLTAGE REGULATOR |
| 9LPR515CGLF | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標準包裝:1 |
| 9LPR515CGLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標準包裝:1,000 |
| 9LPR515CKLF | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標準包裝:1 |
| 9LPR515CKLFT | 功能描述:IC CLOCK MANANGEMENT 制造商:idt, integrated device technology inc 系列:* 零件狀態(tài):最後搶購 標準包裝:1,000 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。