參數(shù)資料
型號: 9LP525BF-2LFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù): 5/21頁
文件大?。?/td> 226K
代理商: 9LP525BF-2LFT
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
13
General SMBus serial interface information for the ICS9LP525-2
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the beginning byte location = N
ICS clock will acknowledge
Controller (host) sends the data byte count = X
ICS clock will acknowledge
Controller (host) starts sending Byte N through
Byte N + X -1
ICS clock will acknowledge each byte one at a time
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the data byte count = X
ICS clock sends Byte N + X -1
ICS clock sends Byte 0 through byte X (if X
(H)
was written to byte 8).
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
P
stoP bit
X
B
y
te
Index Block Write Operation
Slave Address D2(H)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T
starT bit
WR
WRite
RT
Repeat starT
RD
ReaD
Beginning Byte N
Byte N + X - 1
N
Not acknowledge
P
stoP bit
Slave Address D3(H)
Index Block Read Operation
Slave Address D2(H)
Beginning Byte = N
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X
B
y
te
ACK
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