參數(shù)資料
型號(hào): 9LP525BF-2LFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, OTHER CLOCK GENERATOR, PDSO56
封裝: 0.300 INCH, 0.025 INCH PITCH, ROHS COMPLIANT, MO-118, SSOP-56
文件頁數(shù): 3/21頁
文件大小: 226K
代理商: 9LP525BF-2LFT
IDTTM/ICSTM PC MAIN CLOCK
1397—11/08/10
ICS9LP525-2
PC MAIN CLOCK
11
Table 4: Device ID table
0
B8b7
B8b6
B8b5
B8b4
Comment
56 pin TSSOP
Table 5: Slew Rate Selection Table
Bit 1
Bit 0
0
1
0
1
1X (2.0 V/ns)
Slew Rate
HI-Z
0.7X (1.4V/ns)
0.8X (1.6 V/ns)
Table 6. PCI3 Configuration Table
PCI3_CFG1
(Byte 11, bit 7)
PCI3_CFG0
(Byte 11, bit 6)
Low
0 or 1
0
0 = Default
Mid
0 or 1
0
1
High
TME=0
1
0
1
2
High
TME=1
1
3
Table 7. PLL Modes for PCI3 Configurations
Outputs
SSC
Outputs
SSC
Outputs
SSC
0 = Default
CPU/SRC/
PCI
Down
USB
NA
-
100MHz
PLL1
(Table 2
applies)
1
CPU
Down
USB
NA
SRC/PCI
Down
100MHz
PLL3
2
CPU
Center
USB
NA
SRC/PCI
Down
100MHz
PLL3
3
CPU
Center
USB/LAN25
NA
SRC/PCI
Down
25MHz SE
PLL2*
*Note: In Mode 3, Byte 8, bit (1:0) must be set to '1' to enable pin 17,18
Table 8. ME Clock Selection Table
PCIF5/
ITP_EN
iAMT_EN
CPU2_AMT_EN CPU1_AMT_EN
x
1
0
x
1
0
1
0
1
PCI3/CFG0
HW Strap
PCI2/TME
HW Strap
Config Mode
Note: 2 bits are needed since
CFG0 is tri-level input
Config
Mode
PLL1
PLL2
PLL3
CPU2 = iAMT Clock
CPU1 and CPU2 both run in iAMT mode
Reserved
Description
SRC_Main_SE
L
(Byte 0, bit 2)
SRC1
PLL Source
Default, CPU1 = iAMT Clock
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