參數(shù)資料
型號(hào): 9FG104YFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.209 INCH, MO-150N, SSOP-28
文件頁數(shù): 17/17頁
文件大?。?/td> 238K
代理商: 9FG104YFT
IDTTM/ICSTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
0839O—12/03/08
ICS9FG104
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
9
Asserting DIF_STOP# pin stops all DIF outputs that are set to be stoppable after their next transition. When the SMBus
DIF_STOP tri-state bit corresponding to the DIF output of interest is programmed to a '0', DIF output will stop DIF_True =
HIGH and DIF_Complement = LOW. When the SMBus DIF_STOP tri-state bit corresponding to the DIF output of interest is
programmed to a '1', DIFoutputs will be tri-stated.
DIF_STOP# - Assertion (transition from '1' to '0')
With the de-assertion of DIF_STOP# all stopped DIF outputs will resume without a glitch. The maximum latency from the
de-assertion to active outputs is 2 - 6 DIF clock periods. If the control register tristate bit corresponding to the output of
interest is programmed to '1', then the stopped DIF outputs will be driven High within 15nS of DIF_Stop# de-assertion to a
voltage greater than 200mV.
DIF_STOP# - De-assertion (transition from '0' to '1')
DIF_STOP#
DIF
DIF#
DIF_Stop#
Tdrive_DIF_Stop, 15nS >200mV
DIF
DIF#
DIF Internal
相關(guān)PDF資料
PDF描述
9FG104YFLFT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
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