參數(shù)資料
型號: 9FG104DFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.209 INCH, MO-150N, SSOP-28
文件頁數(shù): 12/17頁
文件大?。?/td> 237K
代理商: 9FG104DFT
IDTTM/ICSTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541—12/18/08
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4
Absolute Max
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
VDD + 0.5V
V
VDD_In
3.3V Logic Input Supply Voltage
GND - 0.5
VDD + 0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
85
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 85°C; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Input High Voltage
VIH
3.3 V +/-5%
2
V
DD + 0.3
V1
Input Low Voltage
VIL
3.3 V +/-5%
V
SS - 0.3
0.8
V
1
Input High Current
IIH
VIN = VDD
-5
5
uA
1
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
uA
1
IIL2
VIN = 0 V; Inputs with pull-up
resistors
-200
uA
1
Full Active, CL = Full load;
f = 400 MHz
125
150
mA
1
Full Active, CL = Full load;
f = 100 MHz
110
125
mA
1
All outputs stopped driven
106
120
mA
1
All outputs stopped Hi-Z
48
60
mA
1
Input Frequency
3
Fi
VDD = 3.3 V
14
25
MHz
3
Pin Inductance
1
Lpin
7nH
1
CIN
Logic Inputs
1.5
5
pF
1
COUT
Output pin capacitance
6
pF
1
Clk Stabilization
1,2
TSTAB
From VDD Power-Up and after
input clock stabilization to 1st
clock
1.8
ms
1,2
Modulation Frequency
fMOD
Triangular Modulation
30
33
kHz
1
DIF output enable
tDIFOE
DIF output enable after
DIF_Stop# de-assertion
15
ns
1
Input Rise and Fall times
tR/tF
20% to 80% of VDD
5
ns
1
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REFOUT pin and tuned to 0 PPM to meet
ppm frequency accuracy on PLL outputs.
Input/Output
Capacitance
1
Input Low Current
IDD3.3STOP
IDD3.3OP
Operating Supply Current
相關PDF資料
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