參數(shù)資料
型號: 9FG104DFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘產(chǎn)生/分配
英文描述: 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
封裝: 0.209 INCH, MO-150N, SSOP-28
文件頁數(shù): 11/17頁
文件大?。?/td> 237K
代理商: 9FG104DFT
IDTTM/ICSTM
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541—12/18/08
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
3
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
XIN/CLKIN
IN
Crystal input or Reference Clock input
2
X2
OUT
Crystal output, Nominally 14.318MHz
3
VDD
PWR
Power supply, nominal 3.3V
4
GND
PWR
Ground pin.
5
REFOUT
OUT
Reference Clock output
6
**FS2
IN
Frequency select pin.
7
DIF_3
OUT
0.7V differential true clock output
8
DIF_3#
OUT
0.7V differential Complementary clock output
9
VDD
PWR
Power supply, nominal 3.3V
10
GND
PWR
Ground pin.
11
DIF_2
OUT
0.7V differential true clock output
12
DIF_2#
OUT
0.7V differential Complementary clock output
13
SDATA
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
14
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
15
DIF_STOP#
IN
Active low input to stop differential output clocks.
16
**SPREAD
IN
Asynchronous, active high input to enable spread spectrum functionality.
17
*SEL14M_25M#
IN
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz, 0 = 25 MHz
18
DIF_1#
OUT
0.7V differential Complementary clock output
19
DIF_1
OUT
0.7V differential true clock output
20
GND
PWR
Ground pin.
21
VDD
PWR
Power supply, nominal 3.3V
22
DIF_0#
OUT
0.7V differential Complementary clock output
23
DIF_0
OUT
0.7V differential true clock output
24
**FS1
I/O
Frequency select pin.
25
**FS0
IN
Frequency select pin.
26
IREF
OUT
This pin establishes the reference current for the differential current-mode output
pairs. This pin requires a fixed precision resistor tied to ground in order to establish
the appropriate current. 475 ohms is the standard value.
27
GNDA
PWR
Ground pin for the PLL core.
28
VDDA
PWR
3.3V power for the PLL core.
相關PDF資料
PDF描述
9FG104YGT 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28
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