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參數(shù)資料
| 型號： | 9EX21831AKLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 21831 SERIES, PLL BASED CLOCK DRIVER, 18 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC72 |
| 封裝： | ROHS COMPLIANT, PLASTIC, MLF-72 |
| 文件頁數(shù)： | 15/17頁 |
| 文件大?。?/td> | 179K |
| 代理商： | 9EX21831AKLF |
IDT
Eighteen Output Differential Buffer w/2 input mux for PCIe Gen3
1678A—07/13/10
9EX21831
Eighteen Output Differential Buffer w/2 input mux for PCIe Gen3
7
Electrical Characteristics - Skew and Differential Jitter Parameters
TA = 0 - 70°C; Supply Voltage VDD/VDDA = 3.3 V +/-5%,
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
NOTES
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
900 1000 1125
ps
1,2,4,5,8
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
4000 4700 5200
ns
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
|250| |350|
ps
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSPO_BYP
Input-to-Output Skew Varation in Bypass mode
across voltage and temperature
|800| |900|
ps
1,2,3,5,8
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9EX devices in Hi BW Mode
25
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSSTE
Random Differential Spread Spectrum Tracking
error beween two 9EX devices in Hi BW Mode
20
75
ps
1,2,3,5,8
DIF{x:0]
tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
100
150
ps
1,2,3,8
PLL Jitter Peaking
jpeak-hibw
LOBW#_BYPASS_HIBW = 1
0
2.5
3
dB
7,8
PLL Jitter Peaking
jpeak-lobw
LOBW#_BYPASS_HIBW = 0
0
2
2.5
dB
7,8
PLL Bandwidth
pllHIBW
LOBW#_BYPASS_HIBW = 1
2
3
4
MHz
8,9
PLL Bandwidth
pllLOBW
LOBW#_BYPASS_HIBW = 0
0.7
1
1.4
MHz
8,9
Duty Cycle
tDC
Measured differentially, PLL Mode
45
50
55
%
1
Duty Cycle Distortion
tDCD
Measured differentially, Bypass Mode @100MHz
-2
0
2
%
1,10
PLL mode
30
50
ps1,11
Additive Jitter in Bypass Mode
20
50
ps
1,11
Notes for preceding table:
6.t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
2 Measured from differential cross-point to differential cross-point.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value.
Jitter, Cycle to cycle
tjcyc-cyc
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9EX21831AKLFT | 功能描述:時鐘發(fā)生器及支持產(chǎn)品 RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:QFN-56 |
| 9EZCA0100000000 | 制造商:Eaton Corporation 功能描述:9E 20 & 30 kVA IAC - Tie for 1+1 Redundant with Maintenance Bypass |
| 9F-110 | 制造商:NA 功能描述: |
| 9F33U0 | 制造商:Thomas & Betts 功能描述:30A,PLG,REV,3P3W,DG,U0,600VAC, |
| 9F33U1 | 制造商:Thomas & Betts 功能描述:30A,PLG,REV,2P3W,DG,U1,125V |
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