參數(shù)資料
型號(hào)： 9EPRS488CKLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC72
封裝： ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù)： 2/22頁(yè)
文件大?。?/td> 266K
代理商： 9EPRS488CKLF
10
Integrated
Circuit
Systems, Inc.
ICS9EPRS488
Datasheet
1616—08/20/09
AC Electrical Characteristics - Low-Power DIF Outputs: CPUKG and HTT
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
NOTES
Crossing Point Variation
V
CROSS
Single-ended Measurement
140
mV
1,2,5
Frequency - CPU
fCPU
Spread Specturm On
198.8
200
MHz
1,3
Frequency - HTT
fHTT
Spread Specturm On
99.4
100
MHz
1,3
Long Term Accuracy
ppmSpread Specturm Off
-300
+300
ppm1,11
Rising Edge Slew Rate
SRISE
Differential Measurement
0.5
10
V/ns
1,4
Falling Edge Slew Rate
SFALL
Differential Measurement
0.5
10
V/ns
1,4
Slew Rate Variation
tSLVAR
Single-ended Measurement
20
%
1
CPU, DIF HTT Jitter - Cycle to
Cycle
CPUJC2C
Differential Measurement
150
ps
1,6
Accumulated Jitter
tJACC
See Notes
1
ns
1,7
Peak to Peak Differential Voltage
VD(PK-PK)
Differential Measurement
400
2400
mV
1,8
Differential Voltage
VD
Differential Measurement
200
1200
mV
1,9
Duty Cycle
DCYC
Differential Measurement
45
55
%
1
Amplitude Variation
V
D
Change in VD DC cycle to cycle
-75
75
mV
1,10
CPU[1:0] Skew
CPUSKEW10
Differential Measurement
100
ps
1
Notes on Electrical Characteristics:
1Guaranteed by design and characterization, not 100% tested in production.
3Minimum Frequency is a result of 0.5% down spread spectrum
6 Max difference of t
CYCLE between any two adjacent cycles.
7 Accumulated tjc.over a 10 s time period, measured with JIT2 TIE at 50ps interval.
8 VD(PK-PK) is the overall magnitude of the differential signal.
11 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
2Single-ended measurement at crossing point. Value is maximum – minimum over all time. DC value of common mode is not
10 The difference in magnitude of two adjacent VD_DC measurements. VD_DC is the stable post overshoot and ring-back part of
5 Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK
and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#.
4Differential measurement through the range of ±100 mV, differential signal must remain monotonic and within slew rate spec
when crossing through this region.
9 VD(min) is the amplitude of the ring-back differential measurement, guaranteed by design, that ring-back will not cross 0V VD.
VD(max) is the largest amplitude allowed.
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9EPRS525AGLFT 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 EMBEDDED 56P CK505 COMPATIBLE RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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