參數(shù)資料
型號(hào)： 9EPRS488CKLF
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 微控制器/微處理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQCC72
封裝： ROHS COMPLIANT, PLASTIC, MLF-72
文件頁(yè)數(shù)： 16/22頁(yè)
文件大?。?/td> 266K
代理商： 9EPRS488CKLF
3
Integrated
Circuit
Systems, Inc.
ICS9EPRS488
Datasheet
1616—08/20/09
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
37
VDDSB_SRC_IO
PWR
Power supply for differential SB_SRC outputs, nominal 1.05V to 3.3V
38
VDDSB_SRC
PWR
Supply for SB SRC PLL core, 3.3V nominal
39
SB_SRC0C_LPRS
OUT
Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor
to GND and no 33 ohm series resistor needed
40
SB_SRC0T_LPRS
OUT
True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
41
SB_SRC_SLOW#*
IN
When low, this real-time, level-sensitive input slows down the SB_SRC outputs to a user determined
lower frequency to save power. The default lower frequency is 80 MHz.
0 = Slow Down, 1 = normal operation.
42
CLKREQ4#**
IN
Clock Request pin for SRC4/5 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
43
CLKREQ3#**
IN
Clock Request pin for SRC3 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
44
VDDSATA
PWR
Power supply for SATA core logic, nominal 3.3V
45
SRC6C/SATAC_LPRS
OUT
Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to GND and
no 33 ohm series resistor needed)
46
SRC6T/SATAT_LPRS
OUT
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
47
GNDSATA
GND
Ground pin for the SRC outputs
48
GNDA
GND
Ground for the Analog Core
49
VDDA
PWR
3.3V Power for the Analog Core
50
CLKREQ2#**
IN
Clock Request pin for SRC2 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
51
CLKREQ1#**
IN
Clock Request pin for SRC1 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
52
GNDCPU
GND
Ground pin for the CPU outputs
53
VDDCPU_IO
PWR
Power supply for differential CPU outputs, nominal 1.05V to 3.3V
54
VDDCPU
PWR
Supply for CPU core, 3.3V nominal
55
CPUKG0C_LPRS
OUT
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated
series resistor. (no 33 ohm series resistor needed)
56
CPUKG0T_LPRS
OUT
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
resistor.(no 33 ohm series resistor needed)
57
PD#
IN
Enter /Exit Power Down.
0 = Power Down, 1 = normal operation.
58
GNDHTT
PWR
Ground pin for the HTT outputs
59
HTT0C_LPRS/66M
OUT
Complementary signal of low-power differential push-pull hypertransport clock with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 1.8V single ended
66MHz hyper transport clock
60
HTT0T_LPRS/66M
OUT
True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed) /1.8V single ended 66MHz hyper
transport clock
61
VDDHTT
PWR
Supply for HTT clocks, nominal 3.3V.
62
VDDREF
PWR
Ref, XTAL power supply, nominal 3.3V
63
REF2/SEL_27
OUT
14.318 MHz reference clock, 3.3V/3.3V Latched input to select 27MHz SS and non SS on SRC7
0 = 100MHz differential spreading SRC clock, 1 = 27MHz non-spreading singled clock on pin 4 and
27MHz spread clock on pin 5.
64
REF1/SEL_SATA
I/O
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output
0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock
65
REF0/SEL_HTT66
I/O
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock
Frequency.
0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock
66
GNDREF
GND
Ground pin for the REF outputs.
67
X1
IN
Crystal input, nominally 14.318MHz
68
X2
OUT
Crystal output, nominally 14.318MHz
69
VDD48
PWR
Power pin for the 48MHz outputs and core. 3.3V
70
48MHz_1
OUT
48MHz clock output.
71
48MHz_0
OUT
48MHz clock output.
72
GND48
GND
Ground pin for the 48MHz outputs
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