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參數(shù)資料
| 型號： | 9DBL411BGILFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | LOW SKEW CLOCK DRIVER, PDSO20 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-20 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 85K |
| 代理商： | 9DBL411BGILFT |
IDT Four Output Low Power Differential Buffer for PCI Express for Gen1, Gen2, and QPI
1645B—04/23/10
Advance Information
ICS9DBL411B
Four Output Low Power Differential Buffer for PCI Express Gen1, Gen2, and QPI
3
TSSOP Pin Description
PIN #
(TSSOP)
PIN NAME
PIN TYPE
DESCRIPTION
1OE0#
IN
Output Enable for DIF0 output. Control is as follows:
0 = enabled, 1 = Low-Low
2
DIF_INC
IN
Complement side of differential input clock
3
DIF_INT
IN
True side of differential input clock
4
VDDA
PWR
3.3V Power for the Analog Core
5
GNDA
GND
Ground for the Analog Core
6OE3#
IN
Output Enable for DIF3 output. Control is as follows:
0 = enabled, 1 = Low-Low
7
DIF3C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
8
DIF3T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
9
VDD_IO
PWR
Power supply for low power differential outputs, nominal 1.05V to 3.3V
10
GND
Ground pin
11
DIF2C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
12
DIF2T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
13
OE2#
IN
Output Enable for DIF2 output. Control is as follows:
0 = enabled, 1 = Low-Low
14
DIF1C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
15
DIF1T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
16
OE1#
IN
Output Enable for DIF1 output. Control is as follows:
0 = enabled, 1 = Low-Low
17
GND
Ground pin
18
VDD_IO
PWR
Power supply for low power differential outputs, nominal 1.05V to 3.3V
19
DIF0C_LPR
OUT
Complement clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
20
DIF0T_LPR
OUT
True clock of low power differential clock pair. (no 50ohm shunt resistor to GND needed)
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PDF描述 |
|---|---|
| 9DBL411BKLF | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411BGLFT | LOW SKEW CLOCK DRIVER, PDSO20 |
| 9DBL411BKILFT | LOW SKEW CLOCK DRIVER, PQCC20 |
| 9DBL411BGLF | LOW SKEW CLOCK DRIVER, PDSO20 |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 9DBL411BGLF | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411BGLFT | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411BKILF | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411BKILFT | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DBL411BKLF | 功能描述:時鐘緩沖器 LOW POWER PCIE/QPI w /POWER DOWN FEATURE RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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