參數(shù)資料
型號: 9DB803DFT
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: MO-118, SSOP-48
文件頁數(shù): 19/21頁
文件大?。?/td> 249K
代理商: 9DB803DFT
IDTTM/ICSTM
Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803D
REV G 01/13/09
ICS9DB803D
Eight Output Differential Buffer for PCIe for Gen 2
7
Absolute Max
Electrical Characteristics - Input/Supply/Common Output Parameters
Symbol
Parameter
Min
Max
Units
VDD_A
3.3V Core Supply Voltage
4.6
V
VDD_In
3.3V Logic Supply Voltage
4.6
V
VIL
Input Low Voltage
GND-0.5
V
VIH
Input High Voltage
VDD+0.5V
V
Ts
Storage Temperature
-65
150
°C
Tambient
Ambient Operating Temp
0
70
°C
Tcase
Case Temperature
115
°C
ESD prot
Input ESD protection
human body model
2000
V
TA = -40 - 85°C; VDD = 3.3 V +/-5%; CL =2pF, RS=33.2, RP=49.9, RREF=475
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS NOTES
Current Source Output
Impedance
Zo
1
VO = Vx
3000
1
Voltage HighVHigh
660
850
1,3
Voltage Low
VLow
-150
150
1,3
Max VoltageVovs
1150
1
Min Voltage
Vuds
-300
1
Crossing Voltage (abs)
Vcross(abs)
250
550
mV
1
Crossing Voltage (var)
d-Vcross
Variation of crossing over all edges
140
mV
1
Long Accuracy
ppmsee Tperiod min-max values
0
ppm1,2
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700
ps
1
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700
ps
1
Rise Time Variation
d-tr
125
ps
1
Fall Time Variation
d-tf
125
ps
1
Duty Cycle
dt3
Measurement from differential wavefrom
45
50
55
%
1
Skew
tsk3
VT = 50%
60
ps
1
PLL mode
40
50
ps1,5
BYPASS mode as additive jitter
15
50
ps1,5
PCIe Gen 1 specs
(pk to pk value)
30
86
ps
1,6,7
PCIe Gen 2 specs
(rms value)
2.6
3.1
ps
1,6,7
PCIe Gen 1 specs
(pk to pk value)
40
86
ps
1,6,7
PCIe Gen 2 specs
(rms value)
2.8
3.1
ps
1,6,7
1Guaranteed by design and characterization, not 100% tested in production.
3I
REF = VDD/(3xRR). For RR = 475
(1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50.
4 Applies to Bypass Mode Only
5 Measured from differential waveform
6 See http://www.pcisig.com for complete specs
7 Device driven by HP81134A Pulse Generator
Statistical measurement on single ended signal
using oscilloscope math function.
mV
Measurement on single ended signal using
absolute value.
mV
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK409/CK410/CK505
accuracy requirements. The 9DB403/803 itself does not contribute to ppm error.
tjphasePLL
Jitter, Cycle to cycle
tjcyc-cyc
tjphasebypass
Jitter, Phase
相關(guān)PDF資料
PDF描述
9DB803DGT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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