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參數(shù)資料
| 型號： | 9DB803DFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | MO-118, SSOP-48 |
| 文件頁數(shù)： | 1/21頁 |
| 文件大小： | 249K |
| 代理商： | 9DB803DFT |
ICS9DB803D
IDTTM/ICSTM
Eight Output Differential Buffer for PCIe Gen 2
ICS9DB803D
REV G 01/13/09
Eight Output Differential Buffer for PCIe Gen 2
DATASHEET
1
STOP
LOGIC
SRC_IN
SRC_IN#
DIF(7:0))
CONTROL
LOGIC
BYPASS#/PLL
SDATA
SCLK
PD#
SPREAD
COMPATIBLE
PLL
8
IREF
OE_(7:0)
8
LOCK
SRC_STOP#
HIGH_BW#
M
U
X
Description
Output Features
The 9DB803 is a DB800 Version 2.0 Yellow Cover part with PCI
Express Gen II support. It can be used in PC or embedded
systems to provide outputs that have low cycle-to-cycle jitter
(50ps), low output-to-output skew (100ps), and are PCI Express
Gen 2 compliant. The 9DB803 supports a 1 to 8 output
configuration, taking a spread or non spread differential HCSL
input from a CK410(B) main clock such as 954101 and
932S401, or any other differential HCSL pair. 9DB803 can
generate HCSL or LVDS outputs from 50 to 100MHz in PLL
mode or 50 to 400Mhz in bypass mode. There are two de-
jittering modes available selectable through the HIGH_BW#
input pin, high bandwidth mode provides de-jittering for spread
inputs and low bandwidth mode provides extra de-jittering for
non-spread inputs. The SRC_IN#, PD#, and individual OE real-
time input pins provide completely programmable power
management control.
8 - 0.7V current-mode differential output pairs
Supports zero delay buffer mode and fanout mode
Bandwidth programming available
Funtional Block Diagram
Key Specifications
Outputs cycle-cycle jitter < 50ps
Outputs skew: 50ps
50-100 MHz operation in PLL mode
50-400 MHz operation in Bypass mode
Phase jitter: PCIe Gen1 < 86ps peak to peak
Phase jitter: PCIe Gen2 < 3.1ps rms
48-pin SSOP/TSSOP package
Available in RoHS compliant packaging
Features/Benefits
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread.
Supports undriven differential outputs in PD# and
SRC_STOP# modes for power management.
Note: Polarities shown for OE_INV = 0.
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| 9DB803DGT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB803DGILF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DGILFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DGLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB803DGLFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB823BFLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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