參數(shù)資料
型號(hào)： 9DB803DFILFT
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝： ROHS COMPLIANT, MO-118, SSOP-48
文件頁(yè)數(shù)： 14/21頁(yè)
文件大小： 174K
代理商： 9DB803DFILFT
ICS9DB803D
Eight Output Differential Buffer for PCIe Gen 2
21
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800-345-7015
408-284-8200
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Corporate Headquarters
Integrated Device Technology, Inc.
6024 Silver Creek Valley Road
San Jose, CA 95138
United States
800 345 7015
+408 284 8200 (outside U.S.)
Asia Pacific and Japan
Integrated Device Technology
Singapore (1997) Pte. Ltd.
Reg. No. 199707558G
435 Orchard Road
#20-03 Wisma Atria
Singapore 238877
+65 6 887 5505
Europe
IDT Europe, Limited
Prime House
Barnett Wood Lane
Leatherhead, Surrey
United Kingdom KT22 7DE
+44 1372 363 339
2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT and the IDT logo are trademarks of Integrated
Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks
or registered trademarks used to identify products or services of their respective owners.
Printed in USA
TM
Revision History
Rev.
Issue Date Description
Page #
A
8/15/2006
Updated electrical characteristics for final data sheet
-
B
Added Input Clock Specs
C
2/29/2008
Updated Input Clock Specs
D
3/18/2008
Fixed typo in Input Clock Parameters
E
3/28/2008
Updated Electrical Char tables
F
4/10/2008
Updated Input Clock Specs
G
1/13/2009
Corrected part ordering information
H
10/7/2009
1. Clarified that Vih and Vil values were for Single ended inputs
2. Added Differential Clock input parameters.
3. Updated Electrical Characteristics to add propagation delay and
phase noise information.
4. Added SMBus electrical characteristics
5. Added foot note about DIF input running in order for the SMBus
interface to work
6. Added foot note to Byte 1 about functionality of OE bits and OE
pins.
7. Updated/Reformatted General Description
Various
J
1/27/2011
Updated Termination Figure 4
12
K
5/9/2011
1. Update pin 2 pin-name and pin description from VDD to VDDR. This
highlights that optimal peformance is obtained by treating VDDR as in
analog pin. This is a document update only, there is no silicon change.
Various
相關(guān)PDF資料
PDF描述
9DB803DGILFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DFILF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB803DFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
9DB803DFLF 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB803DFLFT 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB803DGILF 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB803DGILFT 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
9DB803DGLF 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN2 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel
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