參數(shù)資料
型號(hào): 9DB801BGLF
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
封裝: 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48
文件頁(yè)數(shù): 17/20頁(yè)
文件大?。?/td> 277K
代理商: 9DB801BGLF
6
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
The ICS9DB801 follows the Intel DB800 Differential Buffer Specification v2.0. This buffer provides eight PCI-Express SRC
clocks. The ICS9DB801 is driven by a differential input pair from a CK409/CK410 main clock generator, such as the
ICS952601 or ICS954101. It provides ouputs meeting tight cycle-to-cycle jitter (50ps) and output-to-output skew (50ps)
requirements.
General Description
Block Diagram
STOP
LOGIC
SRC_IN
SRC_IN#
DIF(7:0))
CONTROL
LOGIC
BYPASS#/PLL
SDATA
SCLK
PD#
SPREAD
COMPATIBLE
PLL
8
IREF
OE_(7:0)
8
LOCK
SRC_STOP#
HIGH_BW#
M
U
X
Note: Polarities shown for OE_INV = 0.
相關(guān)PDF資料
PDF描述
9DB801CGLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB801CFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB801BFLF 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB801BGLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
9DB801CFLFT 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48
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