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參數(shù)資料
| 型號： | 9DB801BGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 16/20頁 |
| 文件大?。?/td> | 277K |
| 代理商： | 9DB801BGLF |
5
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
25
GND
PWR
Ground pin.
26
PD
IN
Asynchronous active high input pin used to power down the
device. The internal clocks are disabled and the VCO is stopped.
27
SRC_STOP
IN
Active high input to stop SRC outputs.
28
HIGH_BW#
IN
3.3V input for selecting PLL Band Width
0 = High, 1= Low
29
DIF_4#
OUT
0.7V differential complement clock outputs
30
DIF_4
OUT
0.7V differential true clock outputs
31
VDD
PWR
Power supply, nominal 3.3V
32
GND
PWR
Ground pin.
33
DIF_5#
OUT
0.7V differential complement clock outputs
34
DIF_5
OUT
0.7V differential true clock outputs
35
OE5#
IN
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
36
OE6#
IN
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
37
DIF_6#
OUT
0.7V differential complement clock outputs
38
DIF_6
OUT
0.7V differential true clock outputs
39
VDD
PWR
Power supply, nominal 3.3V
40
OE_INV
IN
This latched input selects the polarity of the OE pins.
0 = OE pins active high, 1 = OE pins active low (OE#)
41
DIF_7#
OUT
0.7V differential complement clock outputs
42
DIF_7
OUT
0.7V differential true clock outputs
43
OE4#
IN
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
44
OE7#
IN
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
45
LOCK
OUT
3.3V output indicating PLL Lock Status. This pin goes high when
lock is achieved.
46
IREF
IN
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
47
GNDA
PWR
Ground pin for the PLL core.
48
VDDA
PWR
3.3V power for the PLL core.
Pin Desription for OE_INV = 1
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 9DB801CGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801CFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801BFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801BGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801CFLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9DB801BGLFT | 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB801CFLF | 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB801CFLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Buffer Single 50MHz to 200MHz 48-Pin SSOP T/R 制造商:Integrated Device Technology Inc 功能描述:9DB801CFLFT - Tape and Reel |
| 9DB801CGLF | 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB801CGLFT | 功能描述:時(shí)鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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