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參數資料
| 型號： | 9DB801BFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | ROHS COMPLIANT, MO-153, SSOP-48 |
| 文件頁數： | 15/20頁 |
| 文件大小： | 277K |
| 代理商： | 9DB801BFLFT |
4
Integrated
Circuit
Systems, Inc.
ICS9DB801
1015B—09/07/06
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
SRC_DIV#
IN
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
2
VDD
PWR
Power supply, nominal 3.3V
3
GND
PWR
Ground pin.
4
SRC_IN
IN
0.7 V Differential SRC TRUE input
5
SRC_IN#
IN
0.7 V Differential SRC COMPLEMENTARY input
6OE0#
IN
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
7OE3#
IN
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
8
DIF_0
OUT
0.7V differential true clock outputs
9
DIF_0#
OUT
0.7V differential complement clock outputs
10
GND
PWR
Ground pin.
11
VDD
PWR
Power supply, nominal 3.3V
12
DIF_1
OUT
0.7V differential true clock outputs
13
DIF_1#
OUT
0.7V differential complement clock outputs
14
OE1#
IN
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
15
OE2#
IN
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
16
DIF_2
OUT
0.7V differential true clock outputs
17
DIF_2#
OUT
0.7V differential complement clock outputs
18
GND
PWR
Ground pin.
19
VDD
PWR
Power supply, nominal 3.3V
20
DIF_3
OUT
0.7V differential true clock outputs
21
DIF_3#
OUT
0.7V differential complement clock outputs
22
BYPASS#/PLL
IN
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
23
SCLK
IN
Clock pin of SMBus circuitry, 5V tolerant.
24
SDATA
I/O
Data pin for SMBus circuitry, 5V tolerant.
Pin Desription for OE_INV = 1
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| 9DB801BGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801CGLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801CFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801BFLF | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 9DB801BGLFT | 9DB SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| 9DB801BGLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB801BGLFT | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB801CFLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB801CFLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Buffer Single 50MHz to 200MHz 48-Pin SSOP T/R 制造商:Integrated Device Technology Inc 功能描述:9DB801CFLFT - Tape and Reel |
| 9DB801CGLF | 功能描述:時鐘緩沖器 8 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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