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參數(shù)資料
| 型號： | 9DB403DGLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, ROHS COMPLIANT, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 7/19頁 |
| 文件大小： | 194K |
| 代理商： | 9DB403DGLF |
IDTTM/ICSTM
Four Output Differential Buffer for PCIe Gen 1 and Gen 2
ICS9DB403D
REV N 05/09/11
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
15
Asserting SRC_STOP# causes all DIF outputs to stop after their next transition (if the control register settings allow the output
to stop). When the SRC_STOP# drive bit is ‘0’, the final state of all stopped DIF outputs is DIF = High and DIF# = Low. There
is no change in output drive current. DIF is driven with 6xIREF. DIF# is not driven, but pulled low by the termination. When the
SRC_STOP# drive bit is ‘1’, the final state of all DIF output pins is Low. Both DIF and DIF# are not driven.
SRC_STOP# - Assertion
All stopped differential outputs resume normal operation in a glitch-free manner. The de-assertion latency to active outputs is
2-6 DIF clock periods, with all DIF outputs resuming simultaneously. If the SRC_STOP# drive control bit is ‘1’ (tri-state), all
stopped DIF outputs must be driven High (>200 mV) within 10 ns of de-assertion.
SRC_STOP# - De-assertion (transition from '0' to '1')
The SRC_STOP# signal is an active-low asynchronous input that cleanly stops and starts the DIF outputs. A valid clock must
be present on SRC_IN for this input to work properly. The SRC_STOP# signal is de-bounced and must remain stable for two
consecutive rising edges of DIF# to be recognized as a valid assertion or de-assertion.
SRC_STOP#
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
PWRDWN#
SRC_Stop#
DIF (Free Running)
DIF# (Free Running)
DIF (Stoppable)
DIF# (Stoppable)
1mS
SRC_STOP_1 (SRC_Stop = Driven, PD = Driven)
SRC_STOP_2 (SRC_Stop =Tristate, PD = Driven)
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| 9DB403DGLFT | 功能描述:時鐘緩沖器 4 OUTPUT PCIE GEN1 BUFFER RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
| 9DB403EGILF | 制造商:Integrated Device Technology Inc 功能描述:IDT 9DB403EGILF General Purpose Semiconductors |
| 9DB423B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Four Output Differential Buffer for PCIe Gen 1, Gen 2 and QPI |
| 9DB423BFLF | 功能描述:外圍驅(qū)動器與原件 - PCI 4 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| 9DB423BFLFT | 功能描述:外圍驅(qū)動器與原件 - PCI 4 OUTPUT PCIE GEN2 BUFFER w/QPI RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
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