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參數(shù)資料
| 型號(hào)： | 9DB202CFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 9DB SERIES, PLL BASED CLOCK DRIVER, 2 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO20 |
| 封裝： | 5.30 X 7.20 MM, 1.75 MM HEIGHT, ROHS COMPLIANT, MO-150, SSOP-20 |
| 文件頁數(shù)： | 11/13頁 |
| 文件大?。?/td> | 673K |
| 代理商： | 9DB202CFLF |
IDT / ICS PCI EXPRESS JITTER ATTENUATOR
7
ICS9DB202CG REV B JULY 14, 2006
ICS9DB202
PCI EXPRESS JITTER ATTENUATOR
APPLICATION INFORMATION
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = V
DD
/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and V
DD
= 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
V_REF
R1
1K
C1
0.1u
R2
1K
Single Ended Clock Input
CLK
nCLK
VDD
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. The ICS9DB202 provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL. V
DD and VDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum jitter
performance, power supply isolation is required.
Figure 1 illus-
trates how a 24
resistor along with a 10F and a .01F bypass
capacitor should be connected to each V
DDA pin. The 10 resis-
tor can also be replaced by a ferrite bead.
FIGURE 1. POWER SUPPLY FILTERING
24
V
DDA
10
F
.01
F
3.3V
.01
F
V
DD
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| 9DB202CFLFT | 功能描述:時(shí)鐘緩沖器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Texas Instruments 輸出端數(shù)量:5 最大輸入頻率:40 MHz 傳播延遲（最大值）: 電源電壓-最大:3.45 V 電源電壓-最小:2.375 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LLP-24 封裝:Reel |
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| 9DB202CG | 制造商:Integrated Device Technology Inc 功能描述:9DB202CG - Rail/Tube |
| 9DB202CGLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 2 HCSL Output PCIe Buffer RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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