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參數(shù)資料
| 型號： | 9883 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Umnmanaged Repeater |
| 中文描述： | 高級10/100 Umnmanaged直放站 |
| 文件頁數(shù)： | 32/56頁 |
| 文件大?。?/td> | 719K |
| 代理商： | 9883 |
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LXT9883/9863
—
Advanced 10/100 Unmanaged Repeater
32
Datasheet
Document #: 249115
Revision #: 003
Rev. Date: 08/07/01
4.0
Application Information
4.1
General Design Guidelines
Following generally accepted design practices is essential to minimize noise levels on power and
ground planes. Up to 50mV of noise is considered acceptable. 50mV to 80mV of noise is
considered marginal. High-frequency switching noise can be reduced, and its effects can be
eliminated, by following these simple guidelines throughout the design:
Fill in unused areas of the signal planes with solid copper. Attach them with vias to a VCC or
ground plane that is not located adjacent to the signal layer.
Use ample bulk and decoupling capacitors throughout the design (a .01
μ
F value is
recommended for decoupling caps).
Provide ample power and ground planes.
Provide termination on all high-speed switching signals and clock lines.
Provide impedance matching on long traces to prevent reflections.
Route high-speed signals next to a continuous, unbroken ground plane.
Filter and shield DC-DC converters, oscillators, etc.
Do not route any digital signals between the LXT98x3 and the RJ-45 connectors at the edge of
the board.
Do not extend any circuit power and ground plane past the center of the magnetics or to the
edge of the board. Use this area for chassis ground, or leave it void.
Figure 9. LXT9883 MII Operation
MII
n
_TXD<3:0>
MII
n
_TXEN
MII
n
_TXER
MII
n
_TXCLK
MII
n
_RXCLK
MII
n
_RXD<3:0>
MII
n
_RXDV
MII
n
_RXER
MII
n
_CRS
MII
n
_COL
LXT9883
10/100
MAC
Port 1
Port 2
Port 3
Port 4
Port 5
Ports 1, 2
TP Ports
MII Ports
Port 6
Port 7
Port 8
The two LXT9883 MII ports act
as the PHY side of the MII. An
external MAC sends TX Data to
the LXT9883 to be repeated to
the network. The LXT9883
repeats network data to the MAC
via the RX Data lines.
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