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參數(shù)資料
| 型號： | 9602 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Dual Retriggerable,Resettable One Shots(雙通道可再觸發(fā)可復(fù)位的散粒) |
| 中文描述： | 雙Retriggerable，復(fù)式一個快照（雙通道可再觸發(fā)可復(fù)位的散粒） |
| 文件頁數(shù)： | 3/8頁 |
| 文件大小： | 179K |
| 代理商： | 9602 |
Switching Characteristics
V
CC
e
5V, T
A
e
25
§
C (See Section 1 for Test Waveforms and Output Load)
Symbol
Parameter
Conditions
Military
Commercial
Units
Min
Max
Min
Max
t
PLH
Propagation Delay Time,
Low-to-High Level Output
Negative Trigger Input
to True Output
35
40
ns
t
PHL
Propagation Delay Time,
High-to-Low Level Output
Negative Trigger Input
To Complement Output
C
L
e
15 pF
C
X
e
0
R
X
e
5 k
X
43
48
ns
t
PW
(MIN)
Minimum True Output
Pulse Width
90
100
ns
Minimum Complement
Pulse Width
100
110
t
PW
Pulse Width
R
X
e
10 k
X
C
X
e
1000 pF
3.08
3.76
3.08
3.76
m
s
C
STRAY
Maximum Allowable Wiring
Capacitance
Pins 2, 14 to
GND
50
50
pF
R
X
External Timing Resistor
5
25
5
50
k
X
Logic Diagrams
TL/F/6611–2
Operating Rules
1. An external resistor (R
X
) and external capacitor (C
X
) are
required as shown in the Logic Diagram.
TL/F/6611–3
2. The value of C
X
may vary from 0 to any necessary value
available. If, however, the capacitor has leakages ap-
proaching 3.0
m
A or if stray capacitance from either ter-
minal to ground is more than 50 pF, the timing equations
may not represent the pulse width obtained.
3. The output pulse with (t) is defined as follows:
t
e
K R
X
C
X
1
a
1
R
X
for C
X
l
10
3
pF
K
0.34
where:
R
X
is in k
X
, C
X
is in pF
t is in ns
for C
X
k
10
3
pF, see Figure 1.
for K vs C
X
see Figure 6.
4. If electrolytic type capacitors are to be used, the following
three configurations are recommended:
A. Use with low leakage capacitors:
The normal RC configuration can be used predictably
only if the forward capacitor leakage at 5.0V is less
than 3
m
A, and the inverse capacitor leakage at 1.0V is
less than 5
m
A over the operational temperature
range.
R
k
0.6 R
X
(Max)
TL/F/6611–4
3
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