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參數(shù)資料
| 型號： | 951413CFLF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56 |
| 文件頁數(shù)： | 26/26頁 |
| 文件大?。?/td> | 257K |
| 代理商： | 951413CFLF |
9
Integrated
Circuit
Systems, Inc.
ICS951413
0929D—10/30/06
SMBus Table: Frequency Select Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
FS Source
Latched Input or SMBus
Frequency Select
RW
Latched
Inputs
SMBus
0
Bit 6
CPU FS3
(SS_EN)
CPU Freq Select Bit3
(Spread Enable)
RW
OFF
ON
0
Bit 5
Reserved
RW
Reserved
X
Bit 4
CK410#
CPU Freq Select Bit 4
RW
Latched
Bit 3
Reserved
RW
0
Bit 2
CPU FS_C
CPU Freq Select Bit 2
RW
Latched
Bit 1
CPU FS_B
CPU Freq Select Bit 1
RW
Latched
Bit 0
CPU FS_A
CPU Freq Select Bit 0
RW
Latched
NOTE: Byte 5 Bit 4 must also set to "1" in order to enable spread for SRC and ATIG clocks
SMBus Table: Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
PCICLK0
Output Enable
RW
Disable
Enable
1
Bit 6
CPUCLK2
Output Enable
RW
Disable
Enable
1
Bit 5
USB_48MHz
Output Enable
RW
Disable
Enable
1
Bit 4
REF0
Output Enable
RW
Disable
Enable
1
Bit 3
REF1
Output Enable
RW
Disable
Enable
1
Bit 2
REF2
Output Enable
RW
Disable
Enable
1
Bit 1
CPUCLK0
Output Enable
RW
Disable
Enable
1
Bit 0
CPUCLK1
Output Enable
RW
Disable
Enable
1
SMBus Table: CLKREQB# Output Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
REQBSRC7
CLKREQB# Controls
SRC7
RW
Does not
control
Controls
0
Bit 6
REQBSRC6
CLKREQB# Controls
SRC6
RW
Does not
control
Controls
0
Bit 5
REQBSRC5
CLKREQB# Controls
SRC5
RW
Does not
control
Controls
0
Bit 4
REQBSRC4
CLKREQB# Controls
SRC4
RW
Does not
control
Controls
0
Bit 3
REQBSRC3
CLKREQB# Controls
SRC3
RW
Does not
control
Controls
0
Bit 2
CPU0_Stop_En
0 = CPU is free-run
1 = CPU is stopped by
CPU_STOP#
RW
Free-Run
Stoppable
1
Bit 1
Reserved
RW
Reserved
X
Bit 0
REQBSRC0
CLKREQB# Controls
SRC0
RW
Does not
control
Controls
0
NOTE: CPU0_Stop_En (Byte2, bit 2) only exists in devices with REV ID = 2 or higher
-
34,33
18,19
22,23
24,25
47,46
43,42
Byte 2
12,13
16,17
54
53
52
47,46
Byte 1
50
41,40
4
-
See Table 1: CPU
Frequency Selection
Table
-
Byte 0
-
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| 951413CFLFT | 制造商:Integrated Device Technology Inc 功能描述:Programmable PLL Clock Generator Triple 56-Pin SSOP T/R |
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| 951414-2011309-AR-PT | 功能描述:集管和線殼 14P BD STCK HDR 2R STRT SMT 10U AU RoHS:否 產品種類:1.0MM Rectangular Connectors 產品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector |
| 951414-2011309-AR-TP | 功能描述:集管和線殼 14P BD STCK HDR 2R STRT SMT 10U AU RoHS:否 產品種類:1.0MM Rectangular Connectors 產品類型:Headers - Pin Strip 系列:DF50 觸點類型:Pin (Male) 節(jié)距:1 mm 位置/觸點數(shù)量:16 排數(shù):1 安裝風格:SMD/SMT 安裝角:Right 端接類型:Solder 外殼材料:Liquid Crystal Polymer (LCP) 觸點材料:Brass 觸點電鍍:Gold 制造商:Hirose Connector |
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