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參數(shù)資料
| 型號(hào)： | 951412AFLFT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, 0.025 INCH PITCH, GREEN, MO-118, SSOP-56 |
| 文件頁(yè)數(shù)： | 4/25頁(yè) |
| 文件大小： | 246K |
| 代理商： | 951412AFLFT |
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12
ICS951412
0883L—04/26/06
Electrical Characteristics - K8 Push Pull Differential Pair
TA = 0 - 70°C; VDD = 3.3 V +/-5%; CL =AMD64 Processor Test Load
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP MAX UNITS
NOTES
Rising Edge Rate
δV/δt
210
V/ns
1
Falling Edge Rate
δV/δt
210
V/ns
1
Differential Voltage
VDIFF
0.4
1.25
2.3
V
1
Change in VDIFF_DC
Magnitude
V
DIFF
-150
150
mV
1
Common Mode Voltage
VCM
1.05 1.25 1.45
V
1
Change in Common
Mode Voltage
V
CM
-200
200
mV
1
Jitter, Cycle to cycle
tjcyc-cyc
Measurement from differential
wavefrom. Maximum difference of cycle
time between 2 adjacent cycles.
0
100
200
ps
1
Jitter, Accumulated
tja
Measured using the JIT2 software
package with a Tek 7404 scope.
TIE (Time Interval Error) measurement
technique:
Sample resolution = 50 ps,
Sample Duration = 10 s
-1000
1000
1,2,3
Duty Cycle
dt3
Measurement from differential
wavefrom
45
53
%
1
Output Impedance
RON
Average value during switching
transition. Used for determining series
termination value.
15
35
55
1
Group Skew
tsrc-skew
Measurement from differential
wavefrom
250
ps
1
1Guaranteed by design and characterization, not 100% tested in production.
2 All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz
3 Spread Spectrum is off
Measured at the AMD64 processor's
test load. 0 V +/- 400 mV (differential
measurement)
Measured at the AMD64 processor's
test load. (single-ended measurement)
相關(guān)PDF資料 |
PDF描述 |
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| 951412AGLFT | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 951412BFLF | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 951412AFLF | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 951412AGLF | 220 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 951413CGLF | 400 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 951412AGLF | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin TSSOP Tube |
| 951412AGLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin TSSOP T/R |
| 951412BFLF | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin SSOP Tube |
| 951412BFLFT | 制造商:Integrated Device Technology Inc 功能描述:PLL Clock Synthesizer Dual 56-Pin SSOP T/R |
| 951412BGLF | 功能描述:時(shí)鐘合成器/抖動(dòng)清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel |
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