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參數資料
| 型號： | 9402AVK |
| 廠商： | MICRONAS SEMICONDUCTOR HOLDING AG |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 14 X 14 MM, 2 MM HEIGHT, PLASTIC, MS-022, MQFP-80 |
| 文件頁數： | 47/126頁 |
| 文件大小： | 1673K |
| 代理商： | 9402AVK |
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DATA SHEET
Micronas
Aug. 16, 2004; 6251-552-1DS
27
Fig. 2–37: Image Format behind Memory
For freerun mode the backend part works stand alone
without analyzing the input signals. The clock domains,
input data part and output data part of the IC, are not
synchronized to each other. If the output processing
works in the freerun mode, the output signals of the
OSC are generated depending on I2C-bus settings.
For locked mode the backend part works with a line
locked clock. This means that the front-end and the
backend of the IC are synchronized to each other. The
generation of the controlling signals depends on output
signals from the front-end. This mode will be the
default and the most used mode for standard TV appli-
cations.
With activated vertical freerun mode the phase of the
generated vsync signal has no correlation to the
incoming vsync signal. A hard switch from freerun
mode to locked mode would therefore cause visible
synchronization problems in the deflection unit of the
TV set concerning the vertical picture positioning. To
avoid these problems a circuit is implemented which
synchronizes the freerunning vsync signal to the vsync
derived from the CVBS signal, to enable a soft transi-
tion to locked mode (PDGSR, LPFOPFF). This syn-
chronization is only possible when the number of
CVBS input lines corresponds to the programmed
value of LPFOP.
When no or very weak signal is connected to the
CVBS input, the IC can be configured to automatically
switch into freerunning mode. This stabilizes the dis-
play which may contain OSD information, e.g. during
channel-tune. The configuration, whether the IC
switches to H-freerun, V-freerun or both can be config-
ured by AUTOFRRN
2.5.5.1. HOUT Generator
The HOUT generator has two operation modes, which
can be selected by the parameter HOUTFR. The
HOUT signal is active high for 64 clock cycles
(CLKB36). In the freerunning-mode the HOUT signal is
generated depending on the PPLOP parameter. In the
locked-mode the HOUT signal is locked on the incom-
ing H-Sync signal derived from CVBS. The polarity of
the HOUT signal is programmable by the parameter
HOUTPOL.
2.5.5.2. VOUT Generator
The VOUT generator has two operation modes, which
can be selected by the parameter VOUTFR. In the fre-
erunning-mode (VOUTFR=1) the VOUT signal is gen-
erated depending on the LPFOP parameter.
In the locked-mode the VOUT signal is synchronized
by the incoming V-Sync signal derived from CVBS,
delayed by some lines (OPDEL). During one incoming
V-Sync signal, two VOUT pulses have to be generated.
The polarity of the VOUT signal is programmable by
the parameter VOUTPOL. The VOUT signal is active
high for two output lines..
APPLOP
(active
pixel per
line output)
HSYNC
NALPFOP
(not active
lines output)
ALPFOP
(Active lines
output)
Complete picture area
PPLOP
LPFOP
(lines
output)
(pixel per line output)
Active picture
VSYNC
Table 2–13: Ingenious configurations of the HOUT and VOUT generator
Mode
HOUTFR
VOUTFR
‘H-and-V-locked’ mode
0
‘H-freerunning / V-locked’ mode
1
0
‘H-and V freerunning’ mode
1
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相關代理商/技術參數 |
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